This is an automated email from the git hooks/post-receive script.
tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allyesconfig in repository toolchain/ci/qemu.
from ffa090bc56 target/s390x: fix s390_probe_access to check PAGE_WRITE_ORG [...] adds 5351fb7cb2 hw/block/nvme: fix invalid msix exclusive uninit adds 0cef06d187 Update version for v6.0.0-rc5 release adds 609d759652 Update version for v6.0.0 release adds ccdf06c1db Open 6.1 development tree adds bf559ee402 hw/arm/smmuv3: Support 16K translation granule adds 8196fe9d83 target/arm: Make Thumb store insns UNDEF for Rn==1111 adds 98f96050aa target/arm: Fix mte_checkN adds f8c8a86060 target/arm: Split out mte_probe_int adds 4a09a21345 target/arm: Fix unaligned checks for mte_check1, mte_probe1 adds 09641ef931 test/tcg/aarch64: Add mte-5 adds 28f3250306 target/arm: Replace MTEDESC ESIZE+TSIZE with SIZEM1 adds bd47b61c5e target/arm: Merge mte_check1, mte_checkN adds d304d280b3 target/arm: Rename mte_probe1 to mte_probe adds 4c3310c73f target/arm: Simplify sve mte checking adds 33e74c3172 target/arm: Remove log2_esize parameter to gen_mte_checkN adds a736cbc303 target/arm: Fix decode of align in VLDST_single adds 6a01eab7d8 target/arm: Rename TBFLAG_A32, SCTLR_B adds ae6eb1e9b3 target/arm: Rename TBFLAG_ANY, PSTATE_SS adds a729a46b05 target/arm: Add wrapper macros for accessing tbflags adds 3902bfc6f0 target/arm: Introduce CPUARMTBFlags adds a378206a20 target/arm: Move mode specific TB flags to tb->cs_base adds 5896f39253 target/arm: Move TBFLAG_AM32 bits to the top adds eee81d41ec target/arm: Move TBFLAG_ANY bits to the bottom adds 4479ec30c9 target/arm: Add ALIGN_MEM to TBFLAG_ANY adds 9d486b40e8 target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness adds 37bf7a055f target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64 adds 9565ac4cc7 target/arm: Fix SCTLR_B test for TCGv_i64 load/store adds abe66294e1 target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness adds 4d753eb5fb target/arm: Enforce word alignment for LDRD/STRD adds 824efdf525 target/arm: Enforce alignment for LDA/LDAH/STL/STLH adds 2e1f39e29b target/arm: Enforce alignment for LDM/STM adds c0c7f66087 target/arm: Enforce alignment for RFE adds 2fd0800c68 target/arm: Enforce alignment for SRS adds ad9aeae1a9 target/arm: Enforce alignment for VLDM/VSTM adds 6cd623d166 target/arm: Enforce alignment for VLDR/VSTR adds a8502b37f6 target/arm: Enforce alignment for VLDn (all lanes) adds 7c68c196cf target/arm: Enforce alignment for VLDn/VSTn (multiple) adds 88976ff0a4 target/arm: Enforce alignment for VLDn/VSTn (single) adds dc82164229 target/arm: Use finalize_memop for aa64 gpr load/store adds 4044a3cd1c target/arm: Use finalize_memop for aa64 fpr load/store adds acb07e08d6 target/arm: Enforce alignment for aa64 load-acq/store-rel adds a9e89e539e target/arm: Use MemOp for size + endian in aa64 vector ld/st adds c8f638d99a target/arm: Enforce alignment for aa64 vector LDn/STn (multiple) adds 37abe399df target/arm: Enforce alignment for aa64 vector LDn/STn (single) adds 0ca0f8720a target/arm: Enforce alignment for sve LD1R adds da7e13c00b hw: add compat machines for 6.1 adds a6091108aa hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and [...] adds c3811c08ac Merge remote-tracking branch 'remotes/pmaydell/tags/pull-tar [...] adds d71cc67d68 tests/test-bdrv-graph-mod: add test_parallel_exclusive_write adds e6af4f0e94 tests/test-bdrv-graph-mod: add test_parallel_perm_update adds 397f7cc0c2 tests/test-bdrv-graph-mod: add test_append_greedy_filter adds ae9d441706 block: bdrv_append(): don't consume reference adds 3ca1f32257 block: BdrvChildClass: add .get_parent_aio_context handler adds 228ca37e12 block: drop ctx argument from bdrv_root_attach_child adds 53e96d1e9f block: make bdrv_reopen_{prepare,commit,abort} private adds 8cad15b156 util: add transactions.c adds 3bf416ba0f block: bdrv_refresh_perms: check for parents permissions conflict adds b0defa8356 block: refactor bdrv_child* permission functions adds 83928dc496 block: rewrite bdrv_child_try_set_perm() using bdrv_refresh_perms() adds 3ef45e0242 block: inline bdrv_child_*() permission functions calls adds bd57f8f7f8 block: use topological sort for permission update adds 2513ef5959 block: add bdrv_drv_set_perm transaction action adds b1d2bbeb3a block: add bdrv_list_* permission update functions adds 0978623e0f block: add bdrv_replace_child_safe() transaction action adds 3bb0e2980a block: fix bdrv_replace_node_common adds 548a74c0db block: add bdrv_attach_child_common() transaction action adds aa5a04c7db block: add bdrv_attach_child_noperm() transaction action adds 117caba9fc block: split out bdrv_replace_node_noperm() adds 2272edcfff block: adapt bdrv_append() for inserting filters adds 46541ee579 block: add bdrv_remove_filter_or_cow transaction action adds 3108a15cf0 block: introduce bdrv_drop_filter() adds b75d64b329 block/backup-top: drop .active adds 9397c14fcb block: drop ignore_children for permission update functions adds 332b3a175f block: make bdrv_unset_inherits_from to be a transaction action adds 1e4c797c75 block: make bdrv_refresh_limits() to be a transaction action adds 160333e1fe block: add bdrv_set_backing_noperm() transaction action adds a2aabf8895 block: bdrv_reopen_multiple(): move bdrv_flush to separate p [...] adds 72373e40fb block: bdrv_reopen_multiple: refresh permissions on updated graph adds 058acc4708 block: drop unused permission update functions adds 25409807cf block: inline bdrv_check_perm_common() adds 4954aacea0 block: inline bdrv_replace_child() adds ecb776bd93 block: refactor bdrv_child_set_perm_safe() transaction action adds 2fe5ff56f1 block: rename bdrv_replace_child_safe() to bdrv_replace_child() adds c20555e15f block: refactor bdrv_node_check_perm() adds 35b7f4abd5 block: Add BDRV_O_NO_SHARE for blk_new_open() adds 0b8fb55ce6 qemu-img convert: Unshare write permission for source adds 68bf733653 vhost-user-blk: Fail gracefully on too large queue size adds f38d1ea497 Merge remote-tracking branch 'remotes/kevin/tags/for-upstrea [...] adds d0a263cdd0 qapi/expr: Comment cleanup adds b7341b89c9 qapi/expr.py: Remove 'info' argument from nested check_if_str adds 0f231dcf29 qapi/expr.py: Check for dict instead of OrderedDict adds 59b5556ce8 qapi/expr.py: constrain incoming expression types adds b66c62a2d3 qapi/expr.py: Add assertion for union type 'check_dict' adds 926bb8add7 qapi/expr.py: move string check upwards in check_type adds 4918bb7def qapi/expr.py: Check type of union and alternate 'data' member adds 7a783ce5b5 qapi/expr.py: Add casts in a few select cases adds 538cd41065 qapi/expr.py: Modify check_keys to accept any Collection adds b9ad358aa0 qapi/expr.py: add type hint annotations adds 210fd63104 qapi/expr.py: Consolidate check_if_str calls in check_if adds e42648dccd qapi/expr.py: Remove single-letter variable adds 328e8ca71a qapi/expr.py: enable pylint checks adds 79e4fd14fb qapi/expr: Only explicitly prohibit 'Kind' nor 'List' for ty [...] adds a48653638f qapi/expr.py: Add docstrings adds eab99939a7 qapi/expr.py: Use tuples instead of lists for static data adds e81718c698 qapi/expr: Update authorship and copyright information adds 46f49468c6 qapi/error: Repurpose QAPIError as an abstract base exception class adds b54e07cc46 qapi/error: Use Python3-style super() adds 86cc2ff65a qapi/error: Make QAPISourceError 'col' parameter optional adds ac89761179 qapi/error: assert QAPISourceInfo is not None adds ac6a7d8884 qapi/error.py: move QAPIParseError to parser.py adds 92870cf3af qapi/error.py: enable pylint checks adds 30d0a016e9 qapi/error: Add type hints adds b54626e0b8 qapi/error.py: enable mypy checks adds 8f860d2633 Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi- [...] adds db647703ba exec: Remove accel/tcg/ from include paths adds c7cefe6c66 decodetree: Introduce whex and whexC helpers adds 9f6e2b4d34 decodetree: More use of f-strings adds 60c425f328 decodetree: Add support for 64-bit instructions adds af93ccacc7 decodetree: Extend argument set syntax to allow types adds 53c5433e84 Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-t [...] adds a27c100c23 target/hexagon: translation changes adds 4c82c2b433 target/hexagon: remove unnecessary checks in find_iclass_slots adds 1de468b398 target/hexagon: Change DECODE_MAPPED_REG operand name to OPNUM adds d9099caf04 target/hexagon: fix typo in comment adds 5f261764ce target/hexagon: remove unnecessary semicolons adds d799f8ad08 Hexagon (target/hexagon) TCG generation cleanup adds edf26ade43 Hexagon (target/hexagon) cleanup gen_log_predicated_reg_write_pair adds 2d27cebbf8 Hexagon (target/hexagon) remove unnecessary inline directives adds 7d9ab2021f Hexagon (target/hexagon) use env_archcpu and env_cpu adds 743debbc37 Hexagon (target/hexagon) properly generate TB end for DISAS_ [...] adds 6c677c60ae Hexagon (target/hexagon) decide if pred has been written at [...] adds 92cfa25fd2 Hexagon (target/hexagon) change variables from int to bool w [...] adds 85511161f7 Hexagon (target/hexagon) remove unused carry_from_add64 function adds 8c36752435 Hexagon (target/hexagon) change type of softfloat_roundingmodes adds c0336c87b7 Hexagon (target/hexagon) use softfloat default NaN and tininess adds 1cb532fe45 Hexagon (target/hexagon) replace float32_mul_pow2 with float [...] adds b3f37abdd3 Hexagon (target/hexagon) use softfloat for float-to-int conversions adds 9fe33c0e70 Hexagon (target/hexagon) cleanup ternary operators in semantics adds 80be682844 Hexagon (target/hexagon) cleanup reg_field_info definition adds a33872eb53 Hexagon (target/hexagon) move QEMU_GENERATE to only be on du [...] adds 85580a6557 Hexagon (target/hexagon) compile all debug code adds d934c16d8a Hexagon (target/hexagon) add F2_sfrecipa instruction adds dd8705bdf5 Hexagon (target/hexagon) add F2_sfinvsqrta adds da74cd2dce Hexagon (target/hexagon) add A5_ACS (vacsh) adds 0a65d28693 Hexagon (target/hexagon) add A6_vminub_RdP adds 57d352ac29 Hexagon (target/hexagon) add A4_addp_c/A4_subp_c adds 46ef47e2a7 Hexagon (target/hexagon) circular addressing adds af7f182127 Hexagon (target/hexagon) bit reverse (brev) addressing adds 0d0b91a804 Hexagon (target/hexagon) load and unpack bytes instructions adds 7aa9ffab79 Hexagon (target/hexagon) load into shifted register instructions adds e628c0156b Hexagon (target/hexagon) CABAC decode bin adds 15106f7dc3 Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-h [...] adds bcad139192 hw/isa/piix4: Use qdev_get_gpio_in_named() to get ISA IRQ adds 84c2fdc397 target/mips: Fix CACHEE opcode (CACHE using EVA addressing) adds 298d43c96b target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPG [...] adds bc2eb5ea1b target/mips: Remove spurious LOG_UNIMP of MTHC0 opcode adds df44e81703 target/mips: Migrate missing CPU fields adds 905bdf72a6 target/mips: Make check_cp0_enabled() return a boolean adds 58ecf15d76 target/mips: Simplify meson TCG rules adds 830a72301c target/mips: Move IEEE rounding mode array to new source file adds fed50ffd5c target/mips: Move msa_reset() to new source file adds adbf1be325 target/mips: Make CPU/FPU regnames[] arrays global adds 830b87ea25 target/mips: Optimize CPU/FPU regnames[] arrays adds 4f14ce4bf4 target/mips: Restrict mips_cpu_dump_state() to cpu.c adds 4d169b9cce target/mips: Turn printfpr() macro into a proper function adds 533fc64feb target/mips: Declare mips_env_set_pc() inlined in "internal.h" adds 0debf1400c target/mips: Merge do_translate_address into cpu_mips_transl [...] adds 6f4aec6a6d target/mips: Extract load/store helpers to ldst_helper.c adds 46369b50ee meson: Introduce meson_user_arch source set for arch-specifi [...] adds 6fe25ce587 target/mips: Introduce tcg-internal.h for TCG specific declarations adds 0a31c16c9c target/mips: Add simple user-mode mips_cpu_do_interrupt() adds 8074365fc7 target/mips: Add simple user-mode mips_cpu_tlb_fill() adds 44e3b05005 target/mips: Move cpu_signal_handler definition around adds 85d8da3fea target/mips: Move sysemu specific files under sysemu/ subfolder adds 137f4d87c6 target/mips: Move physical addressing code to sysemu/physaddr.c adds 8b28cde403 target/mips: Restrict cpu_mips_get_random() / update_pagemas [...] adds ad520a9784 target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder adds c284201702 target/mips: Restrict mmu_init() to TCG adds 920b48cc14 target/mips: Move tlb_helper.c to tcg/sysemu/ adds f3185ec2f3 target/mips: Restrict CPUMIPSTLBContext::map_address() handl [...] adds d60146a938 target/mips: Move Special opcodes to tcg/sysemu/special_helper.c adds ecdbcb0a94 target/mips: Move helper_cache() to tcg/sysemu/special_helper.c adds 6575529b65 target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c adds 8aa52bdc87 target/mips: Move exception management code to exception.c adds 5679479b9a target/mips: Move CP0 helpers to sysemu/cp0.c adds a2b0a27d33 target/mips: Move TCG source files under tcg/ sub directory adds db6b6f4dbf hw/mips: Restrict non-virtualized machines to TCG adds 1c13514449 gitlab-ci: Add KVM mips64el cross-build jobs adds e93d8bcf9d Merge remote-tracking branch 'remotes/philmd/tags/mips-20210 [...] adds ca0fd2e345 bsd-user: whitespace changes adds cefbade173 bsd-user: style tweak: keyword space ( adds fa0546370d bsd-user: style tweak: return is not a function, eliminate () adds 92ac45049b bsd-user: put back a break; that had gone missing... adds 58b3beb483 bsd-user: style tweak: Put {} around all if/else/for statements adds 3e13d8e34b Merge remote-tracking branch 'remotes/bsdimp/tags/pull-bsd-u [...]
No new revisions were added by this update.
Summary of changes: .gitlab-ci.d/crossbuilds.yml | 8 + MAINTAINERS | 9 +- VERSION | 2 +- block.c | 1329 ++++++++++++-------- block/backup-top.c | 48 +- block/block-backend.c | 30 +- block/commit.c | 1 + block/file-posix.c | 91 +- block/io.c | 31 +- block/mirror.c | 3 - blockdev.c | 4 - blockjob.c | 11 +- bsd-user/bsdload.c | 55 +- bsd-user/qemu.h | 4 +- bsd-user/syscall.c | 1 + docs/devel/decodetree.rst | 11 +- docs/sphinx/qapidoc.py | 3 +- fpu/softfloat-specialize.c.inc | 3 + hw/arm/smmuv3.c | 6 +- hw/arm/virt.c | 7 +- hw/block/nvme.c | 3 +- hw/block/vhost-user-blk.c | 5 + hw/core/machine.c | 5 + hw/i386/pc.c | 3 + hw/i386/pc_piix.c | 14 +- hw/i386/pc_q35.c | 13 +- hw/isa/piix4.c | 5 +- hw/mips/meson.build | 9 +- hw/pci-host/gpex.c | 56 +- hw/ppc/spapr.c | 15 +- hw/s390x/s390-virtio-ccw.c | 14 +- include/block/block.h | 14 +- include/block/block_int.h | 8 +- include/exec/helper-gen.h | 4 +- include/exec/helper-proto.h | 4 +- include/exec/helper-tcg.h | 4 +- include/hw/boards.h | 3 + include/hw/i386/pc.h | 3 + include/hw/pci-host/gpex.h | 4 + include/qemu/transactions.h | 63 + linux-user/hexagon/cpu_loop.c | 2 +- meson.build | 7 +- qemu-img.c | 2 +- scripts/decodetree.py | 172 +-- scripts/qapi/error.py | 47 +- scripts/qapi/expr.py | 442 +++++-- scripts/qapi/mypy.ini | 10 - scripts/qapi/parser.py | 14 +- scripts/qapi/pylintrc | 4 +- scripts/qapi/schema.py | 4 +- target/arm/cpu.h | 105 +- target/arm/helper-a64.c | 2 +- target/arm/helper-a64.h | 3 +- target/arm/helper.c | 162 +-- target/arm/internals.h | 13 +- target/arm/mte_helper.c | 181 ++- target/arm/neon-ls.decode | 4 +- target/arm/sve_helper.c | 100 +- target/arm/translate-a64.c | 236 ++-- target/arm/translate-a64.h | 2 +- target/arm/translate-neon.c.inc | 117 +- target/arm/translate-sve.c | 11 +- target/arm/translate-vfp.c.inc | 20 +- target/arm/translate.c | 270 ++-- target/arm/translate.h | 38 + target/hexagon/arch.c | 181 ++- target/hexagon/arch.h | 9 +- target/hexagon/conv_emu.c | 177 --- target/hexagon/conv_emu.h | 31 - target/hexagon/cpu.c | 14 +- target/hexagon/cpu.h | 5 - target/hexagon/cpu_bits.h | 2 +- target/hexagon/decode.c | 84 +- target/hexagon/fma_emu.c | 40 +- target/hexagon/gen_tcg.h | 424 ++++++- target/hexagon/gen_tcg_funcs.py | 2 +- target/hexagon/genptr.c | 233 +++- target/hexagon/helper.h | 23 +- target/hexagon/iclass.c | 4 - target/hexagon/imported/alu.idef | 44 + target/hexagon/imported/compare.idef | 12 +- target/hexagon/imported/encode_pp.def | 30 + target/hexagon/imported/float.idef | 32 + target/hexagon/imported/ldst.idef | 68 + target/hexagon/imported/macros.def | 47 + target/hexagon/imported/shift.idef | 47 + target/hexagon/insn.h | 21 +- target/hexagon/internal.h | 11 +- target/hexagon/macros.h | 118 +- target/hexagon/meson.build | 1 - target/hexagon/op_helper.c | 392 ++++-- target/hexagon/reg_fields.c | 3 +- target/hexagon/reg_fields.h | 4 +- target/hexagon/translate.c | 175 ++- target/hexagon/translate.h | 9 +- target/mips/cpu.c | 281 +---- target/mips/fpu.c | 25 + target/mips/helper.h | 183 +-- target/mips/internal.h | 107 +- target/mips/meson.build | 53 +- target/mips/msa.c | 60 + target/mips/op_helper.c | 1210 ------------------ target/mips/{ => sysemu}/addr.c | 0 target/mips/sysemu/cp0.c | 123 ++ target/mips/{ => sysemu}/cp0_timer.c | 0 target/mips/{ => sysemu}/machine.c | 21 +- target/mips/sysemu/meson.build | 7 + target/mips/sysemu/physaddr.c | 257 ++++ target/mips/{ => tcg}/dsp_helper.c | 0 target/mips/tcg/exception.c | 167 +++ target/mips/{ => tcg}/fpu_helper.c | 8 - target/mips/tcg/ldst_helper.c | 288 +++++ target/mips/{ => tcg}/lmmi_helper.c | 0 target/mips/{ => tcg}/meson.build | 39 +- target/mips/{ => tcg}/mips32r6.decode | 0 target/mips/{ => tcg}/mips64r6.decode | 0 target/mips/{ => tcg}/msa32.decode | 0 target/mips/{ => tcg}/msa64.decode | 0 target/mips/{ => tcg}/msa_helper.c | 36 - target/mips/{ => tcg}/msa_helper.h.inc | 0 target/mips/{ => tcg}/msa_translate.c | 0 target/mips/{ => tcg}/mxu_translate.c | 0 target/mips/tcg/op_helper.c | 420 +++++++ target/mips/{ => tcg}/rel6_translate.c | 0 target/mips/{ => tcg/sysemu}/cp0_helper.c | 0 target/mips/tcg/sysemu/meson.build | 6 + target/mips/{ => tcg/sysemu}/mips-semi.c | 0 target/mips/tcg/sysemu/special_helper.c | 173 +++ target/mips/{ => tcg/sysemu}/tlb_helper.c | 623 ++++----- target/mips/tcg/sysemu_helper.h.inc | 185 +++ target/mips/tcg/tcg-internal.h | 64 + target/mips/{ => tcg}/translate.c | 115 +- target/mips/{ => tcg}/translate_addr_const.c | 0 target/mips/{ => tcg}/tx79.decode | 0 target/mips/{ => tcg}/tx79_translate.c | 0 target/mips/{ => tcg}/txx9_translate.c | 0 target/mips/tcg/user/meson.build | 3 + target/mips/tcg/user/tlb_helper.c | 64 + target/mips/translate.h | 7 +- tests/decode/succ_argset_type1.decode | 1 + tests/qapi-schema/alternate-data-invalid.err | 2 + tests/qapi-schema/alternate-data-invalid.json | 4 + .../qapi-schema/alternate-data-invalid.out | 0 tests/qapi-schema/meson.build | 2 + tests/qapi-schema/union-invalid-data.err | 2 + tests/qapi-schema/union-invalid-data.json | 6 + .../qapi-schema/union-invalid-data.out | 0 tests/qemu-iotests/245 | 2 +- tests/qemu-iotests/283.out | 2 +- tests/qemu-iotests/tests/qsd-jobs.out | 2 +- tests/tcg/aarch64/Makefile.target | 2 +- tests/tcg/aarch64/mte-5.c | 44 + tests/tcg/hexagon/Makefile.target | 6 + tests/tcg/hexagon/brev.c | 190 +++ tests/tcg/hexagon/circ.c | 486 +++++++ tests/tcg/hexagon/fpstuff.c | 242 ++++ tests/tcg/hexagon/load_align.c | 415 ++++++ tests/tcg/hexagon/load_unpack.c | 474 +++++++ tests/tcg/hexagon/misc.c | 47 + tests/tcg/hexagon/multi_result.c | 282 +++++ tests/unit/test-bdrv-drain.c | 2 +- tests/unit/test-bdrv-graph-mod.c | 209 ++- util/meson.build | 1 + util/transactions.c | 96 ++ 164 files changed, 8869 insertions(+), 4292 deletions(-) create mode 100644 include/qemu/transactions.h delete mode 100644 target/hexagon/conv_emu.c delete mode 100644 target/hexagon/conv_emu.h create mode 100644 target/mips/fpu.c create mode 100644 target/mips/msa.c delete mode 100644 target/mips/op_helper.c rename target/mips/{ => sysemu}/addr.c (100%) create mode 100644 target/mips/sysemu/cp0.c rename target/mips/{ => sysemu}/cp0_timer.c (100%) rename target/mips/{ => sysemu}/machine.c (94%) create mode 100644 target/mips/sysemu/meson.build create mode 100644 target/mips/sysemu/physaddr.c rename target/mips/{ => tcg}/dsp_helper.c (100%) create mode 100644 target/mips/tcg/exception.c rename target/mips/{ => tcg}/fpu_helper.c (99%) create mode 100644 target/mips/tcg/ldst_helper.c rename target/mips/{ => tcg}/lmmi_helper.c (100%) copy target/mips/{ => tcg}/meson.build (50%) rename target/mips/{ => tcg}/mips32r6.decode (100%) rename target/mips/{ => tcg}/mips64r6.decode (100%) rename target/mips/{ => tcg}/msa32.decode (100%) rename target/mips/{ => tcg}/msa64.decode (100%) rename target/mips/{ => tcg}/msa_helper.c (99%) rename target/mips/{ => tcg}/msa_helper.h.inc (100%) rename target/mips/{ => tcg}/msa_translate.c (100%) rename target/mips/{ => tcg}/mxu_translate.c (100%) create mode 100644 target/mips/tcg/op_helper.c rename target/mips/{ => tcg}/rel6_translate.c (100%) rename target/mips/{ => tcg/sysemu}/cp0_helper.c (100%) create mode 100644 target/mips/tcg/sysemu/meson.build rename target/mips/{ => tcg/sysemu}/mips-semi.c (100%) create mode 100644 target/mips/tcg/sysemu/special_helper.c rename target/mips/{ => tcg/sysemu}/tlb_helper.c (76%) create mode 100644 target/mips/tcg/sysemu_helper.h.inc create mode 100644 target/mips/tcg/tcg-internal.h rename target/mips/{ => tcg}/translate.c (99%) rename target/mips/{ => tcg}/translate_addr_const.c (100%) rename target/mips/{ => tcg}/tx79.decode (100%) rename target/mips/{ => tcg}/tx79_translate.c (100%) rename target/mips/{ => tcg}/txx9_translate.c (100%) create mode 100644 target/mips/tcg/user/meson.build create mode 100644 target/mips/tcg/user/tlb_helper.c create mode 100644 tests/decode/succ_argset_type1.decode create mode 100644 tests/qapi-schema/alternate-data-invalid.err create mode 100644 tests/qapi-schema/alternate-data-invalid.json copy scripts/codeconverter/codeconverter/__init__.py => tests/qapi-schema/alternat [...] create mode 100644 tests/qapi-schema/union-invalid-data.err create mode 100644 tests/qapi-schema/union-invalid-data.json copy scripts/codeconverter/codeconverter/__init__.py => tests/qapi-schema/union-in [...] create mode 100644 tests/tcg/aarch64/mte-5.c create mode 100644 tests/tcg/hexagon/brev.c create mode 100644 tests/tcg/hexagon/circ.c create mode 100644 tests/tcg/hexagon/load_align.c create mode 100644 tests/tcg/hexagon/load_unpack.c create mode 100644 tests/tcg/hexagon/multi_result.c create mode 100644 util/transactions.c