[Tcwg-commits] [gcc] branch devel/c++-coroutines updated (81481378b33 -> cf4440f646f)

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unknown user pushed a change to branch devel/c++-coroutines in repository gcc.

from 81481378b33 Merge master r10-7228. adds cd0b7124273 c++: Fix parsing of invalid enum specifiers [PR90995] adds 046c58907ec c: Handle C_TYPE_INCOMPLETE_VARS even for ENUMERAL_TYPEs [PR94172] adds 2e30d3e3e88 testsuite: Fix g++.dg/debug/dwarf2/const2b.C target selector adds 3b2cc34369a Daily bump. adds 98f29f5638f libstdc++: Fix type-erasure in experimental::net::executor [...] adds 80616e5b7a5 c++: Fix comment typo. adds 52b3aa8be18 dwarf: Generate DIEs for external variables with -g1 [93751] adds af8656be8df c++: Diagnose a deduction guide in a wrong scope [PR91759] adds 4e3d3e40726 middle-end/94188 fix fold of addr expression generation adds 4da9288745d libgomp testsuite - disable long double for AMDGCN adds cb26919c857 aarch64: Treat p12-p15 as call-preserved in SVE PCS functions adds d91480dee93 aarch64: Fix SYMBOL_TINY_GOT handling for ILP32 [PR94201] adds d5029d45940 Fix up duplicated duplicated words in comments adds 1ba9acb11e3 middle-end/94206 fix memset folding to avoid types with padding adds 11cf25c40e3 PR c++/94147 - mangling of lambdas assigned to globals adds 5a80a6c3e5f amdgcn: Add cond_add/sub/and/ior/xor for all vector modes adds dbde9e2d595 amdgcn: Fix vector compare modes adds 07522ae90b5 libstdc++: Fix compilation with released versions of Clang adds e5de406f996 libstdc++ Fix compilation of <stop_token> with Clang adds 0db2cd17702 analyzer: tweaks to exploded_node ctor adds 7d9c107ab1e analyzer: introduce noop_region_model_context adds f665beeba62 analyzer: add test coverage for fixed ICE [PR94047] adds 884d9141112 analyzer: make summarized dumps more comprehensive adds 26cbcfe5fce Fix libgomp.oacc-fortran/atomic_capture-1.f90 adds 8165795c155 [ARM][GCC][2/3x]: MVE intrinsics with ternary operands. adds e3678b4464a [ARM][GCC][3/3x]: MVE intrinsics with ternary operands. adds db5db9d2548 [ARM][GCC][1/4x]: MVE intrinsics with quaternary operands. adds 8eb3b6b9cf2 [ARM][GCC][2/4x]: MVE intrinsics with quaternary operands. adds f2170a379b0 [ARM][GCC][3/4x]: MVE intrinsics with quaternary operands. adds 532e9e2402a [ARM][GCC][4/4x]: MVE intrinsics with quaternary operands. adds 4ff68575991 [ARM][GCC][1/5x]: MVE store intrinsics. adds 535a8645bb8 [ARM][GCC][2/5x]: MVE load intrinsics. adds 405e918c314 [ARM][GCC][3/5x]: MVE store intrinsics with predicated suffix. adds 429d607bc46 [ARM][GCC][4/5x]: MVE load intrinsics with zero(_z) suffix. adds bf1e3d5afa1 [ARM][GCC][5/5x]: MVE ACLE load intrinsics which load a byt [...] adds 4cc23303bad [ARM][GCC][6/5x]: Remaining MVE load intrinsics which loads [...] adds 5cad47e0f85 [ARM][GCC][7/5x]: MVE store intrinsics which stores byte,ha [...] adds 7a5fffa5ed0 [ARM][GCC][8/5x]: Remaining MVE store intrinsics which stor [...] new cf4440f646f Merge master r10-7266.

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Summary of changes: gcc/ChangeLog | 3382 ++++ gcc/DATESTAMP | 2 +- gcc/analyzer/ChangeLog | 55 + gcc/analyzer/diagnostic-manager.cc | 2 +- gcc/analyzer/engine.cc | 13 +- gcc/analyzer/exploded-graph.h | 7 +- gcc/analyzer/region-model.cc | 265 +- gcc/analyzer/region-model.h | 90 +- gcc/analyzer/sm-malloc.cc | 2 +- gcc/asan.c | 7 +- gcc/c/ChangeLog | 17 + gcc/c/c-decl.c | 50 +- gcc/c/c-tree.h | 12 +- gcc/c/c-typeck.c | 3 +- gcc/config/aarch64/aarch64.c | 48 +- gcc/config/aarch64/aarch64.md | 22 +- gcc/config/arc/arc.c | 2 +- gcc/config/arm/arm-builtins.c | 188 + gcc/config/arm/arm-protos.h | 1 + gcc/config/arm/arm.c | 25 + gcc/config/arm/arm_mve.h | 16961 ++++++++++++++++--- gcc/config/arm/arm_mve_builtins.def | 506 + gcc/config/arm/constraints.md | 16 +- gcc/config/arm/mve.md | 6415 ++++++- gcc/config/arm/predicates.md | 16 + gcc/config/gcn/gcn-valu.md | 31 +- gcc/config/gcn/gcn.h | 4 + gcc/cp/ChangeLog | 31 + gcc/cp/constraint.cc | 8 +- gcc/cp/coroutines.cc | 4 +- gcc/cp/decl.c | 9 + gcc/cp/logic.cc | 8 +- gcc/cp/parser.c | 72 +- gcc/cp/pt.c | 2 +- gcc/cp/tree.c | 20 +- gcc/d/ChangeLog | 6 + gcc/d/d-target.cc | 2 +- gcc/d/expr.cc | 2 +- gcc/dwarf2out.c | 70 +- gcc/fold-const.c | 7 +- gcc/fortran/ChangeLog | 6 + gcc/fortran/class.c | 2 +- gcc/fortran/trans-types.c | 2 +- gcc/gimple-fold.c | 10 +- gcc/gimple-loop-versioning.cc | 2 +- gcc/ipa-predicate.c | 2 +- gcc/optinfo-emit-json.cc | 2 +- gcc/testsuite/ChangeLog | 1387 +- .../c-c++-common/goacc/firstprivate-mappings-1.c | 12 +- gcc/testsuite/g++.dg/abi/lambda-vis.C | 23 + gcc/testsuite/g++.dg/abi/mangle74.C | 30 + gcc/testsuite/g++.dg/cpp0x/enum40.C | 26 + gcc/testsuite/g++.dg/cpp1z/class-deduction72.C | 11 + gcc/testsuite/g++.dg/debug/dwarf2/const2b.C | 2 +- .../g++.dg/goacc/firstprivate-mappings-1.C | 12 +- gcc/testsuite/gcc.dg/analyzer/pr94047.c | 23 + gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-1.c | 6 + gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-2.c | 6 + gcc/testsuite/gcc.dg/pr94172-1.c | 12 + gcc/testsuite/gcc.dg/pr94172-2.c | 19 + gcc/testsuite/gcc.dg/pr94188.c | 10 + gcc/testsuite/gcc.dg/torture/pr94206.c | 17 + .../gcc.target/aarch64/{pr78255.c => pr94201.c} | 5 +- .../gcc.target/aarch64/sve/acle/general/cpy_1.c | 4 + gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c | 6 + .../gcc.target/aarch64/sve/pcs/saves_1_be_nowrap.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_1_be_wrap.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_1_le_nowrap.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_1_le_wrap.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c | 304 +- .../gcc.target/aarch64/sve/pcs/saves_2_be_wrap.c | 304 +- .../gcc.target/aarch64/sve/pcs/saves_2_le_nowrap.c | 304 +- .../gcc.target/aarch64/sve/pcs/saves_2_le_wrap.c | 304 +- .../gcc.target/aarch64/sve/pcs/saves_4_be.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_4_le.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_5_be.c | 76 +- .../gcc.target/aarch64/sve/pcs/saves_5_le.c | 76 +- .../gcc.target/aarch64/sve/pcs/stack_clash_1.c | 81 +- .../aarch64/sve/pcs/stack_clash_1_1024.c | 82 +- .../gcc.target/aarch64/sve/pcs/stack_clash_1_128.c | 78 +- .../aarch64/sve/pcs/stack_clash_1_2048.c | 80 +- .../gcc.target/aarch64/sve/pcs/stack_clash_1_256.c | 82 +- .../gcc.target/aarch64/sve/pcs/stack_clash_1_512.c | 82 +- .../aarch64/sve/pcs/stack_clash_2_1024.c | 66 +- .../aarch64/sve/pcs/stack_clash_2_2048.c | 66 +- .../gcc.target/aarch64/sve/pcs/stack_clash_2_256.c | 66 +- .../gcc.target/aarch64/sve/pcs/stack_clash_2_512.c | 66 +- .../gcc.target/arm/mve/intrinsics/vabavq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_u8.c | 24 + .../{vcvtq_m_f16_s16.c => vabsq_m_f16.c} | 10 +- .../{vcvtq_m_f32_s32.c => vabsq_m_f32.c} | 10 +- .../intrinsics/{vbicq_m_n_s16.c => vabsq_m_s16.c} | 10 +- .../intrinsics/{vbicq_m_n_s32.c => vabsq_m_s32.c} | 10 +- .../intrinsics/{vbicq_m_n_s16.c => vabsq_m_s8.c} | 14 +- .../gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vbicq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbicq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbicq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbicq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbicq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vbicq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbicq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbicq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_m_f16.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_m_f32.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_m_s16.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_m_s32.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_m_s8.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_m_u16.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_m_u32.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_m_u8.c | 24 + .../arm/mve/intrinsics/vcaddq_rot90_m_f16.c | 24 + .../arm/mve/intrinsics/vcaddq_rot90_m_f32.c | 24 + .../arm/mve/intrinsics/vcaddq_rot90_m_s16.c | 24 + .../arm/mve/intrinsics/vcaddq_rot90_m_s32.c | 24 + .../arm/mve/intrinsics/vcaddq_rot90_m_s8.c | 24 + .../arm/mve/intrinsics/vcaddq_rot90_m_u16.c | 24 + .../arm/mve/intrinsics/vcaddq_rot90_m_u32.c | 24 + .../arm/mve/intrinsics/vcaddq_rot90_m_u8.c | 24 + .../intrinsics/{vbicq_m_n_s16.c => vclsq_m_s16.c} | 10 +- .../intrinsics/{vbicq_m_n_s32.c => vclsq_m_s32.c} | 10 +- .../intrinsics/{vbicq_m_n_s16.c => vclsq_m_s8.c} | 14 +- .../intrinsics/{vbicq_m_n_s16.c => vclzq_m_s16.c} | 10 +- .../intrinsics/{vbicq_m_n_s32.c => vclzq_m_s32.c} | 10 +- .../intrinsics/{vbicq_m_n_s16.c => vclzq_m_s8.c} | 14 +- .../intrinsics/{vbicq_m_n_u16.c => vclzq_m_u16.c} | 10 +- .../intrinsics/{vbicq_m_n_u32.c => vclzq_m_u32.c} | 10 +- .../intrinsics/{vbicq_m_n_s32.c => vclzq_m_u8.c} | 14 +- .../gcc.target/arm/mve/intrinsics/vcmlaq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmlaq_f32.c | 22 + .../{vcvtq_m_f16_s16.c => vcmlaq_m_f16.c} | 11 +- .../{vcvtq_m_f32_s32.c => vcmlaq_m_f32.c} | 11 +- .../arm/mve/intrinsics/vcmlaq_rot180_f16.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot180_f32.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot180_m_f16.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot180_m_f32.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot270_f16.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot270_f32.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot270_m_f16.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot270_m_f32.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot90_f16.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot90_f32.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot90_m_f16.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot90_m_f32.c | 24 + .../intrinsics/{vctp16q_m.c => vcmpcsq_m_n_u16.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpcsq_m_n_u32.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpcsq_m_n_u8.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpcsq_m_u16.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpcsq_m_u32.c} | 10 +- .../mve/intrinsics/{vctp16q_m.c => vcmpcsq_m_u8.c} | 10 +- .../{vcmpeqq_m_f16.c => vcmpeqq_m_n_f16.c} | 6 +- .../{vcmpeqq_m_f32.c => vcmpeqq_m_n_f32.c} | 6 +- .../intrinsics/{vctp16q_m.c => vcmpeqq_m_n_s16.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpeqq_m_n_s32.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpeqq_m_n_s8.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpeqq_m_n_u16.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpeqq_m_n_u32.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpeqq_m_n_u8.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpeqq_m_s16.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpeqq_m_s32.c} | 10 +- .../mve/intrinsics/{vctp16q_m.c => vcmpeqq_m_s8.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpeqq_m_u16.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpeqq_m_u32.c} | 10 +- .../mve/intrinsics/{vctp16q_m.c => vcmpeqq_m_u8.c} | 10 +- .../{vcmpeqq_m_f16.c => vcmpgeq_m_f16.c} | 4 +- .../{vcmpeqq_m_f32.c => vcmpgeq_m_f32.c} | 4 +- .../{vcmpeqq_m_f16.c => vcmpgeq_m_n_f16.c} | 8 +- .../{vcmpeqq_m_f32.c => vcmpgeq_m_n_f32.c} | 8 +- .../intrinsics/{vctp16q_m.c => vcmpgeq_m_n_s16.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpgeq_m_n_s32.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpgeq_m_n_s8.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpgeq_m_s16.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpgeq_m_s32.c} | 10 +- .../mve/intrinsics/{vctp16q_m.c => vcmpgeq_m_s8.c} | 10 +- .../{vcmpeqq_m_f16.c => vcmpgtq_m_f16.c} | 4 +- .../{vcmpeqq_m_f32.c => vcmpgtq_m_f32.c} | 4 +- .../{vcmpeqq_m_f16.c => vcmpgtq_m_n_f16.c} | 8 +- .../{vcmpeqq_m_f32.c => vcmpgtq_m_n_f32.c} | 8 +- .../intrinsics/{vctp16q_m.c => vcmpgtq_m_n_s16.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpgtq_m_n_s32.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpgtq_m_n_s8.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpgtq_m_s16.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpgtq_m_s32.c} | 10 +- .../mve/intrinsics/{vctp16q_m.c => vcmpgtq_m_s8.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmphiq_m_n_u16.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmphiq_m_n_u32.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmphiq_m_n_u8.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmphiq_m_u16.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmphiq_m_u32.c} | 10 +- .../mve/intrinsics/{vctp16q_m.c => vcmphiq_m_u8.c} | 10 +- .../{vcmpeqq_m_f16.c => vcmpleq_m_f16.c} | 4 +- .../{vcmpeqq_m_f32.c => vcmpleq_m_f32.c} | 4 +- .../{vcmpeqq_m_f16.c => vcmpleq_m_n_f16.c} | 8 +- .../{vcmpeqq_m_f32.c => vcmpleq_m_n_f32.c} | 8 +- .../intrinsics/{vctp16q_m.c => vcmpleq_m_n_s16.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpleq_m_n_s32.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpleq_m_n_s8.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpleq_m_s16.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpleq_m_s32.c} | 10 +- .../mve/intrinsics/{vctp16q_m.c => vcmpleq_m_s8.c} | 10 +- .../{vcmpeqq_m_f16.c => vcmpltq_m_f16.c} | 4 +- .../{vcmpeqq_m_f32.c => vcmpltq_m_f32.c} | 4 +- .../{vcmpeqq_m_f16.c => vcmpltq_m_n_f16.c} | 8 +- .../{vcmpeqq_m_f32.c => vcmpltq_m_n_f32.c} | 8 +- .../intrinsics/{vctp16q_m.c => vcmpltq_m_n_s16.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpltq_m_n_s32.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpltq_m_n_s8.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpltq_m_s16.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpltq_m_s32.c} | 10 +- .../mve/intrinsics/{vctp16q_m.c => vcmpltq_m_s8.c} | 10 +- .../gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c | 2 +- .../{vcmpeqq_m_f16.c => vcmpneq_m_f16.c} | 4 +- .../{vcmpeqq_m_f32.c => vcmpneq_m_f32.c} | 4 +- .../{vcmpeqq_m_f16.c => vcmpneq_m_n_f16.c} | 8 +- .../{vcmpeqq_m_f32.c => vcmpneq_m_n_f32.c} | 8 +- .../intrinsics/{vctp16q_m.c => vcmpneq_m_n_s16.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpneq_m_n_s32.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpneq_m_n_s8.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpneq_m_n_u16.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpneq_m_n_u32.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpneq_m_n_u8.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpneq_m_s16.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpneq_m_s32.c} | 10 +- .../mve/intrinsics/{vctp16q_m.c => vcmpneq_m_s8.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpneq_m_u16.c} | 10 +- .../intrinsics/{vctp16q_m.c => vcmpneq_m_u32.c} | 10 +- .../mve/intrinsics/{vctp16q_m.c => vcmpneq_m_u8.c} | 10 +- .../gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c | 24 + .../arm/mve/intrinsics/vcmulq_rot180_m_f16.c | 24 + .../arm/mve/intrinsics/vcmulq_rot180_m_f32.c | 24 + .../arm/mve/intrinsics/vcmulq_rot270_m_f16.c | 24 + .../arm/mve/intrinsics/vcmulq_rot270_m_f32.c | 24 + .../arm/mve/intrinsics/vcmulq_rot90_m_f16.c | 24 + .../arm/mve/intrinsics/vcmulq_rot90_m_f32.c | 24 + .../{vcvtq_m_f16_s16.c => vcvtbq_m_f16_f32.c} | 10 +- .../{vcvtq_m_f32_s32.c => vcvtbq_m_f32_f16.c} | 10 +- .../{vcvtaq_m_s16_f16.c => vcvtmq_m_s16_f16.c} | 6 +- .../{vcvtaq_m_s32_f32.c => vcvtmq_m_s32_f32.c} | 6 +- .../{vcvtaq_m_u16_f16.c => vcvtmq_m_u16_f16.c} | 6 +- .../{vcvtaq_m_u32_f32.c => vcvtmq_m_u32_f32.c} | 6 +- .../{vcvtaq_m_s16_f16.c => vcvtnq_m_s16_f16.c} | 6 +- .../{vcvtaq_m_s32_f32.c => vcvtnq_m_s32_f32.c} | 6 +- .../{vcvtaq_m_u16_f16.c => vcvtnq_m_u16_f16.c} | 6 +- .../{vcvtaq_m_u32_f32.c => vcvtnq_m_u32_f32.c} | 6 +- .../{vcvtaq_m_s16_f16.c => vcvtpq_m_s16_f16.c} | 6 +- .../{vcvtaq_m_s32_f32.c => vcvtpq_m_s32_f32.c} | 6 +- .../{vcvtaq_m_u16_f16.c => vcvtpq_m_u16_f16.c} | 6 +- .../{vcvtaq_m_u32_f32.c => vcvtpq_m_u32_f32.c} | 6 +- .../{vcvtq_m_f16_s16.c => vcvtq_m_n_f16_s16.c} | 5 +- .../{vcvtq_m_f16_u16.c => vcvtq_m_n_f16_u16.c} | 5 +- .../{vcvtq_m_f32_s32.c => vcvtq_m_n_f32_s32.c} | 5 +- .../{vcvtq_m_f32_u32.c => vcvtq_m_n_f32_u32.c} | 5 +- .../{vcvtaq_m_s16_f16.c => vcvtq_m_n_s16_f16.c} | 7 +- .../{vcvtaq_m_s32_f32.c => vcvtq_m_n_s32_f32.c} | 7 +- .../{vcvtaq_m_u16_f16.c => vcvtq_m_n_u16_f16.c} | 7 +- .../{vcvtaq_m_u32_f32.c => vcvtq_m_n_u32_f32.c} | 7 +- .../{vcvtaq_m_s16_f16.c => vcvtq_m_s16_f16.c} | 6 +- .../{vcvtaq_m_s32_f32.c => vcvtq_m_s32_f32.c} | 6 +- .../{vcvtaq_m_u16_f16.c => vcvtq_m_u16_f16.c} | 6 +- .../{vcvtaq_m_u32_f32.c => vcvtq_m_u32_f32.c} | 6 +- .../{vcvtq_m_f16_s16.c => vcvttq_m_f16_f32.c} | 10 +- .../{vcvtq_m_f32_s32.c => vcvttq_m_f32_f16.c} | 10 +- .../{vcvtq_m_f16_s16.c => vdupq_m_n_f16.c} | 10 +- .../{vcvtq_m_f32_s32.c => vdupq_m_n_f32.c} | 10 +- .../{vbicq_m_n_s16.c => vdupq_m_n_s16.c} | 10 +- .../{vbicq_m_n_s32.c => vdupq_m_n_s32.c} | 10 +- .../intrinsics/{vbicq_m_n_s16.c => vdupq_m_n_s8.c} | 14 +- .../{vbicq_m_n_u16.c => vdupq_m_n_u16.c} | 10 +- .../{vbicq_m_n_u32.c => vdupq_m_n_u32.c} | 10 +- .../intrinsics/{vbicq_m_n_s32.c => vdupq_m_n_u8.c} | 14 +- .../gcc.target/arm/mve/intrinsics/veorq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmaq_f32.c | 22 + .../{vcvtq_m_f16_s16.c => vfmaq_m_f16.c} | 11 +- .../{vcvtq_m_f32_s32.c => vfmaq_m_f32.c} | 11 +- .../{vcvtq_m_f16_s16.c => vfmaq_m_n_f16.c} | 11 +- .../{vcvtq_m_f32_s32.c => vfmaq_m_n_f32.c} | 11 +- .../gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c | 22 + .../{vcvtq_m_f16_s16.c => vfmasq_m_n_f16.c} | 11 +- .../{vcvtq_m_f32_s32.c => vfmasq_m_n_f32.c} | 11 +- .../gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmsq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmsq_f32.c | 22 + .../{vcvtq_m_f16_s16.c => vfmsq_m_f16.c} | 11 +- .../{vcvtq_m_f32_s32.c => vfmsq_m_f32.c} | 11 +- .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot270_m_s16.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot270_m_s32.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot270_m_s8.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot90_m_s16.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot90_m_s32.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot90_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c | 24 + .../intrinsics/{vcvtq_n_f16_s16.c => vld1q_f16.c} | 12 +- .../intrinsics/{vcvtq_n_f32_s32.c => vld1q_f32.c} | 12 +- .../mve/intrinsics/{vandq_s16.c => vld1q_s16.c} | 12 +- .../mve/intrinsics/{vandq_s32.c => vld1q_s32.c} | 12 +- .../arm/mve/intrinsics/{vabsq_s8.c => vld1q_s8.c} | 12 +- .../mve/intrinsics/{vclzq_u16.c => vld1q_u16.c} | 12 +- .../mve/intrinsics/{vclzq_u32.c => vld1q_u32.c} | 12 +- .../arm/mve/intrinsics/{vclzq_u8.c => vld1q_u8.c} | 12 +- .../arm/mve/intrinsics/vldrbq_gather_offset_s16.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_s32.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_s8.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_u16.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_u32.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_u8.c | 22 + .../mve/intrinsics/vldrbq_gather_offset_z_s16.c | 22 + .../mve/intrinsics/vldrbq_gather_offset_z_s32.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c | 22 + .../mve/intrinsics/vldrbq_gather_offset_z_u16.c | 22 + .../mve/intrinsics/vldrbq_gather_offset_z_u32.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c | 22 + .../intrinsics/{vcreateq_s16.c => vldrbq_s16.c} | 6 +- .../intrinsics/{vcreateq_s32.c => vldrbq_s32.c} | 6 +- .../mve/intrinsics/{vdupq_n_s8.c => vldrbq_s8.c} | 6 +- .../intrinsics/{vcreateq_u16.c => vldrbq_u16.c} | 6 +- .../mve/intrinsics/{vbicq_n_u32.c => vldrbq_u32.c} | 6 +- .../mve/intrinsics/{vcreateq_u8.c => vldrbq_u8.c} | 6 +- .../intrinsics/{vcreateq_s16.c => vldrbq_z_s16.c} | 6 +- .../intrinsics/{vcreateq_s32.c => vldrbq_z_s32.c} | 6 +- .../intrinsics/{vcreateq_s8.c => vldrbq_z_s8.c} | 6 +- .../intrinsics/{vcreateq_u16.c => vldrbq_z_u16.c} | 6 +- .../intrinsics/{vbicq_n_u32.c => vldrbq_z_u32.c} | 6 +- .../intrinsics/{vcreateq_u8.c => vldrbq_z_u8.c} | 6 +- .../{vcreateq_s16.c => vldrdq_gather_base_s64.c} | 8 +- .../{vcreateq_u16.c => vldrdq_gather_base_u64.c} | 8 +- .../{vcreateq_s16.c => vldrdq_gather_base_z_s64.c} | 8 +- .../{vcreateq_u16.c => vldrdq_gather_base_z_u64.c} | 8 +- .../arm/mve/intrinsics/vldrdq_gather_offset_s64.c | 22 + .../arm/mve/intrinsics/vldrdq_gather_offset_u64.c | 22 + .../mve/intrinsics/vldrdq_gather_offset_z_s64.c | 22 + .../mve/intrinsics/vldrdq_gather_offset_z_u64.c | 22 + .../intrinsics/vldrdq_gather_shifted_offset_s64.c | 22 + .../intrinsics/vldrdq_gather_shifted_offset_u64.c | 22 + .../vldrdq_gather_shifted_offset_z_s64.c | 22 + .../vldrdq_gather_shifted_offset_z_u64.c | 22 + .../intrinsics/{vcvtq_f16_u16.c => vldrhq_f16.c} | 6 +- .../arm/mve/intrinsics/vldrhq_gather_offset_f16.c | 22 + .../arm/mve/intrinsics/vldrhq_gather_offset_s16.c | 22 + .../arm/mve/intrinsics/vldrhq_gather_offset_s32.c | 22 + .../arm/mve/intrinsics/vldrhq_gather_offset_u16.c | 22 + .../arm/mve/intrinsics/vldrhq_gather_offset_u32.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_f16.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_s16.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_s32.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_u16.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_u32.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_f16.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_s16.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_s32.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_u16.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_u32.c | 22 + .../vldrhq_gather_shifted_offset_z_f16.c | 22 + .../vldrhq_gather_shifted_offset_z_s16.c | 22 + .../vldrhq_gather_shifted_offset_z_s32.c | 22 + .../vldrhq_gather_shifted_offset_z_u16.c | 22 + .../vldrhq_gather_shifted_offset_z_u32.c | 22 + .../intrinsics/{vcreateq_s16.c => vldrhq_s16.c} | 6 +- .../intrinsics/{vcreateq_s32.c => vldrhq_s32.c} | 6 +- .../intrinsics/{vcreateq_u16.c => vldrhq_u16.c} | 6 +- .../intrinsics/{vcreateq_u32.c => vldrhq_u32.c} | 6 +- .../{vcvtbq_f16_f32.c => vldrhq_z_f16.c} | 6 +- .../intrinsics/{vcreateq_s16.c => vldrhq_z_s16.c} | 6 +- .../intrinsics/{vcreateq_s32.c => vldrhq_z_s32.c} | 6 +- .../intrinsics/{vcreateq_u16.c => vldrhq_z_u16.c} | 6 +- .../intrinsics/{vbicq_n_u32.c => vldrhq_z_u32.c} | 6 +- .../intrinsics/{vcreateq_f32.c => vldrwq_f32.c} | 6 +- .../{vcreateq_f32.c => vldrwq_gather_base_f32.c} | 6 +- .../{vcreateq_s32.c => vldrwq_gather_base_s32.c} | 6 +- .../{vbicq_n_u32.c => vldrwq_gather_base_u32.c} | 6 +- .../{vcreateq_f32.c => vldrwq_gather_base_z_f32.c} | 6 +- .../{vcreateq_s32.c => vldrwq_gather_base_z_s32.c} | 6 +- .../{vbicq_n_u32.c => vldrwq_gather_base_z_u32.c} | 6 +- .../arm/mve/intrinsics/vldrwq_gather_offset_f32.c | 22 + .../arm/mve/intrinsics/vldrwq_gather_offset_s32.c | 22 + .../arm/mve/intrinsics/vldrwq_gather_offset_u32.c | 22 + .../mve/intrinsics/vldrwq_gather_offset_z_f32.c | 22 + .../mve/intrinsics/vldrwq_gather_offset_z_s32.c | 22 + .../mve/intrinsics/vldrwq_gather_offset_z_u32.c | 22 + .../intrinsics/vldrwq_gather_shifted_offset_f32.c | 22 + .../intrinsics/vldrwq_gather_shifted_offset_s32.c | 22 + .../intrinsics/vldrwq_gather_shifted_offset_u32.c | 22 + .../vldrwq_gather_shifted_offset_z_f32.c | 22 + .../vldrwq_gather_shifted_offset_z_s32.c | 22 + .../vldrwq_gather_shifted_offset_z_u32.c | 22 + .../intrinsics/{vcreateq_s32.c => vldrwq_s32.c} | 6 +- .../intrinsics/{vcreateq_u32.c => vldrwq_u32.c} | 6 +- .../intrinsics/{vcreateq_f32.c => vldrwq_z_f32.c} | 6 +- .../intrinsics/{vcreateq_s32.c => vldrwq_z_s32.c} | 6 +- .../intrinsics/{vbicq_n_u32.c => vldrwq_z_u32.c} | 6 +- .../intrinsics/{vbicq_m_n_u16.c => vmaxaq_m_s16.c} | 10 +- .../intrinsics/{vbicq_m_n_u32.c => vmaxaq_m_s32.c} | 10 +- .../intrinsics/{vbicq_m_n_s32.c => vmaxaq_m_s8.c} | 14 +- .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c | 22 + .../{vcmpeqq_m_f16.c => vmaxnmaq_m_f16.c} | 10 +- .../{vcmpeqq_m_f32.c => vmaxnmaq_m_f32.c} | 10 +- .../arm/mve/intrinsics/vmaxnmavq_p_f16.c | 22 + .../arm/mve/intrinsics/vmaxnmavq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c | 22 + .../intrinsics/{vbicq_m_n_u16.c => vminaq_m_s16.c} | 10 +- .../intrinsics/{vbicq_m_n_u32.c => vminaq_m_s32.c} | 10 +- .../intrinsics/{vbicq_m_n_s32.c => vminaq_m_s8.c} | 14 +- .../gcc.target/arm/mve/intrinsics/vminavq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminavq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminavq_p_s8.c | 22 + .../{vcmpeqq_m_f16.c => vminnmaq_m_f16.c} | 10 +- .../{vcmpeqq_m_f32.c => vminnmaq_m_f32.c} | 10 +- .../arm/mve/intrinsics/vminnmavq_p_f16.c | 22 + .../arm/mve/intrinsics/vminnmavq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vminvq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_u8.c | 22 + .../arm/mve/intrinsics/vmladavaq_p_s16.c | 23 + .../arm/mve/intrinsics/vmladavaq_p_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c | 23 + .../arm/mve/intrinsics/vmladavaq_p_u16.c | 23 + .../arm/mve/intrinsics/vmladavaq_p_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmladavaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_s8.c | 22 + .../intrinsics/{vabavq_u16.c => vmladavaq_u16.c} | 8 +- .../intrinsics/{vabavq_u32.c => vmladavaq_u32.c} | 8 +- .../mve/intrinsics/{vabavq_u8.c => vmladavaq_u8.c} | 8 +- .../arm/mve/intrinsics/vmladavaxq_p_s16.c | 23 + .../arm/mve/intrinsics/vmladavaxq_p_s32.c | 23 + .../arm/mve/intrinsics/vmladavaxq_p_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c | 22 + .../arm/mve/intrinsics/vmladavxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmladavxq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c | 22 + .../arm/mve/intrinsics/vmlaldavaq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlaldavaq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlaldavaq_p_u16.c | 22 + .../arm/mve/intrinsics/vmlaldavaq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c | 22 + .../{vrmlaldavhaq_s32.c => vmlaldavaq_s32.c} | 8 +- .../gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c | 22 + .../{vrmlaldavhaq_u32.c => vmlaldavaq_u32.c} | 8 +- .../arm/mve/intrinsics/vmlaldavaxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_p_u16.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_p_u32.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_s16.c | 22 + .../{vrmlaldavhaq_s32.c => vmlaldavaxq_s32.c} | 8 +- .../arm/mve/intrinsics/vmlaldavq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlaldavq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlaldavq_p_u16.c | 22 + .../arm/mve/intrinsics/vmlaldavq_p_u32.c | 22 + .../arm/mve/intrinsics/vmlaldavxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlaldavxq_p_s32.c | 22 + .../{vbicq_m_n_s16.c => vmlaq_m_n_s16.c} | 11 +- .../{vbicq_m_n_s32.c => vmlaq_m_n_s32.c} | 11 +- .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c | 24 + .../{vbicq_m_n_u16.c => vmlaq_m_n_u16.c} | 11 +- .../{vbicq_m_n_u32.c => vmlaq_m_n_u32.c} | 11 +- .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c | 22 + .../{vbicq_m_n_s16.c => vmlasq_m_n_s16.c} | 11 +- .../{vbicq_m_n_s32.c => vmlasq_m_n_s32.c} | 11 +- .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c | 24 + .../{vbicq_m_n_u16.c => vmlasq_m_n_u16.c} | 11 +- .../{vbicq_m_n_u32.c => vmlasq_m_n_u32.c} | 11 +- .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c | 22 + .../arm/mve/intrinsics/vmlsdavaq_p_s16.c | 23 + .../arm/mve/intrinsics/vmlsdavaq_p_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c | 22 + .../arm/mve/intrinsics/vmlsdavaxq_p_s16.c | 23 + .../arm/mve/intrinsics/vmlsdavaxq_p_s32.c | 23 + .../arm/mve/intrinsics/vmlsdavaxq_p_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c | 22 + .../arm/mve/intrinsics/vmlsdavxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsdavxq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c | 22 + .../arm/mve/intrinsics/vmlsldavaq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsldavaq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c | 22 + .../{vrmlaldavhaq_s32.c => vmlsldavaq_s32.c} | 8 +- .../arm/mve/intrinsics/vmlsldavaxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsldavaxq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlsldavaxq_s16.c | 22 + .../{vrmlaldavhaq_s32.c => vmlsldavaxq_s32.c} | 8 +- .../arm/mve/intrinsics/vmlsldavq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsldavq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlsldavxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsldavxq_p_s32.c | 22 + .../{vbicq_m_n_s32.c => vmovlbq_m_s16.c} | 10 +- .../intrinsics/{vbicq_m_n_s16.c => vmovlbq_m_s8.c} | 10 +- .../{vbicq_m_n_u32.c => vmovlbq_m_u16.c} | 10 +- .../intrinsics/{vbicq_m_n_u16.c => vmovlbq_m_u8.c} | 10 +- .../{vbicq_m_n_s32.c => vmovltq_m_s16.c} | 10 +- .../intrinsics/{vbicq_m_n_s16.c => vmovltq_m_s8.c} | 10 +- .../{vbicq_m_n_u32.c => vmovltq_m_u16.c} | 10 +- .../intrinsics/{vbicq_m_n_u16.c => vmovltq_m_u8.c} | 10 +- .../{vbicq_m_n_s16.c => vmovnbq_m_s16.c} | 14 +- .../{vbicq_m_n_s16.c => vmovnbq_m_s32.c} | 10 +- .../{vbicq_m_n_s32.c => vmovnbq_m_u16.c} | 14 +- .../{vbicq_m_n_u16.c => vmovnbq_m_u32.c} | 10 +- .../{vbicq_m_n_s16.c => vmovntq_m_s16.c} | 14 +- .../{vbicq_m_n_s16.c => vmovntq_m_s32.c} | 10 +- .../{vbicq_m_n_s32.c => vmovntq_m_u16.c} | 14 +- .../{vbicq_m_n_u16.c => vmovntq_m_u32.c} | 10 +- .../gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_s16.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_s32.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_s8.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_u16.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_u32.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_u8.c | 24 + .../arm/mve/intrinsics/vmullbq_poly_m_p16.c | 24 + .../arm/mve/intrinsics/vmullbq_poly_m_p8.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_s16.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_s32.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_s8.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_u16.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_u32.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_u8.c | 24 + .../arm/mve/intrinsics/vmulltq_poly_m_p16.c | 24 + .../arm/mve/intrinsics/vmulltq_poly_m_p8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_u8.c | 24 + .../{vbicq_m_n_s16.c => vmvnq_m_n_s16.c} | 10 +- .../{vbicq_m_n_s32.c => vmvnq_m_n_s32.c} | 10 +- .../{vbicq_m_n_u16.c => vmvnq_m_n_u16.c} | 10 +- .../{vbicq_m_n_u32.c => vmvnq_m_n_u32.c} | 10 +- .../intrinsics/{vbicq_m_n_s16.c => vmvnq_m_s16.c} | 10 +- .../intrinsics/{vbicq_m_n_s32.c => vmvnq_m_s32.c} | 10 +- .../intrinsics/{vbicq_m_n_s16.c => vmvnq_m_s8.c} | 14 +- .../intrinsics/{vbicq_m_n_u16.c => vmvnq_m_u16.c} | 10 +- .../intrinsics/{vbicq_m_n_u32.c => vmvnq_m_u32.c} | 10 +- .../intrinsics/{vbicq_m_n_s32.c => vmvnq_m_u8.c} | 14 +- .../{vcvtq_m_f16_s16.c => vnegq_m_f16.c} | 10 +- .../{vcvtq_m_f32_s32.c => vnegq_m_f32.c} | 10 +- .../intrinsics/{vbicq_m_n_s16.c => vnegq_m_s16.c} | 10 +- .../intrinsics/{vbicq_m_n_s32.c => vnegq_m_s32.c} | 10 +- .../intrinsics/{vbicq_m_n_s16.c => vnegq_m_s8.c} | 14 +- .../gcc.target/arm/mve/intrinsics/vornq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vornq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vornq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vornq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vornq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vornq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vornq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vornq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vorrq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vorrq_m_f32.c | 24 + .../{vbicq_m_n_s16.c => vorrq_m_n_s16.c} | 6 +- .../{vbicq_m_n_s32.c => vorrq_m_n_s32.c} | 6 +- .../{vbicq_m_n_u16.c => vorrq_m_n_u16.c} | 6 +- .../{vbicq_m_n_u32.c => vorrq_m_n_u32.c} | 6 +- .../gcc.target/arm/mve/intrinsics/vorrq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vorrq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vorrq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vorrq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vorrq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vorrq_m_u8.c | 24 + .../intrinsics/{vcmpeqq_m_f16.c => vpselq_f16.c} | 13 +- .../intrinsics/{vcmpeqq_m_f32.c => vpselq_f32.c} | 13 +- .../gcc.target/arm/mve/intrinsics/vpselq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_s64.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_u64.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_u8.c | 22 + .../intrinsics/{vbicq_m_n_s16.c => vqabsq_m_s16.c} | 10 +- .../intrinsics/{vbicq_m_n_s32.c => vqabsq_m_s32.c} | 10 +- .../intrinsics/{vbicq_m_n_s16.c => vqabsq_m_s8.c} | 14 +- .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c | 24 + .../arm/mve/intrinsics/vqdmladhq_m_s16.c | 24 + .../arm/mve/intrinsics/vqdmladhq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c | 22 + .../arm/mve/intrinsics/vqdmladhxq_m_s16.c | 24 + .../arm/mve/intrinsics/vqdmladhxq_m_s32.c | 24 + .../arm/mve/intrinsics/vqdmladhxq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c | 22 + .../{vbicq_m_n_s16.c => vqdmlahq_m_n_s16.c} | 11 +- .../{vbicq_m_n_s32.c => vqdmlahq_m_n_s32.c} | 11 +- .../arm/mve/intrinsics/vqdmlahq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_u8.c | 22 + .../arm/mve/intrinsics/vqdmlsdhq_m_s16.c | 24 + .../arm/mve/intrinsics/vqdmlsdhq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c | 22 + .../arm/mve/intrinsics/vqdmlsdhxq_m_s16.c | 24 + .../arm/mve/intrinsics/vqdmlsdhxq_m_s32.c | 24 + .../arm/mve/intrinsics/vqdmlsdhxq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c | 22 + .../arm/mve/intrinsics/vqdmulhq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqdmulhq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqdmulhq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c | 24 + .../arm/mve/intrinsics/vqdmullbq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqdmullbq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqdmullbq_m_s16.c | 24 + .../arm/mve/intrinsics/vqdmullbq_m_s32.c | 24 + .../arm/mve/intrinsics/vqdmulltq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqdmulltq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqdmulltq_m_s16.c | 24 + .../arm/mve/intrinsics/vqdmulltq_m_s32.c | 24 + .../{vbicq_m_n_s16.c => vqmovnbq_m_s16.c} | 14 +- .../{vbicq_m_n_s16.c => vqmovnbq_m_s32.c} | 10 +- .../{vbicq_m_n_s32.c => vqmovnbq_m_u16.c} | 14 +- .../{vbicq_m_n_u16.c => vqmovnbq_m_u32.c} | 10 +- .../{vbicq_m_n_s16.c => vqmovntq_m_s16.c} | 14 +- .../{vbicq_m_n_s16.c => vqmovntq_m_s32.c} | 10 +- .../{vbicq_m_n_s32.c => vqmovntq_m_u16.c} | 14 +- .../{vbicq_m_n_u16.c => vqmovntq_m_u32.c} | 10 +- .../{vbicq_m_n_s32.c => vqmovunbq_m_s16.c} | 14 +- .../{vbicq_m_n_u16.c => vqmovunbq_m_s32.c} | 10 +- .../{vbicq_m_n_s32.c => vqmovuntq_m_s16.c} | 14 +- .../{vbicq_m_n_u16.c => vqmovuntq_m_s32.c} | 10 +- .../intrinsics/{vbicq_m_n_s16.c => vqnegq_m_s16.c} | 10 +- .../intrinsics/{vbicq_m_n_s32.c => vqnegq_m_s32.c} | 10 +- .../intrinsics/{vbicq_m_n_s16.c => vqnegq_m_s8.c} | 14 +- .../arm/mve/intrinsics/vqrdmladhq_m_s16.c | 24 + .../arm/mve/intrinsics/vqrdmladhq_m_s32.c | 24 + .../arm/mve/intrinsics/vqrdmladhq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c | 22 + .../arm/mve/intrinsics/vqrdmladhxq_m_s16.c | 24 + .../arm/mve/intrinsics/vqrdmladhxq_m_s32.c | 24 + .../arm/mve/intrinsics/vqrdmladhxq_m_s8.c | 24 + .../arm/mve/intrinsics/vqrdmladhxq_s16.c | 22 + .../arm/mve/intrinsics/vqrdmladhxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c | 22 + .../arm/mve/intrinsics/vqrdmlahq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqrdmlahq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqrdmlahq_m_n_s8.c | 24 + .../arm/mve/intrinsics/vqrdmlahq_n_s16.c | 22 + .../arm/mve/intrinsics/vqrdmlahq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c | 22 + .../arm/mve/intrinsics/vqrdmlahq_n_u16.c | 22 + .../arm/mve/intrinsics/vqrdmlahq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u8.c | 22 + .../arm/mve/intrinsics/vqrdmlashq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqrdmlashq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqrdmlashq_m_n_s8.c | 24 + .../arm/mve/intrinsics/vqrdmlashq_n_s16.c | 22 + .../arm/mve/intrinsics/vqrdmlashq_n_s32.c | 22 + .../arm/mve/intrinsics/vqrdmlashq_n_s8.c | 22 + .../arm/mve/intrinsics/vqrdmlashq_n_u16.c | 22 + .../arm/mve/intrinsics/vqrdmlashq_n_u32.c | 22 + .../arm/mve/intrinsics/vqrdmlashq_n_u8.c | 22 + .../arm/mve/intrinsics/vqrdmlsdhq_m_s16.c | 24 + .../arm/mve/intrinsics/vqrdmlsdhq_m_s32.c | 24 + .../arm/mve/intrinsics/vqrdmlsdhq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c | 22 + .../arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c | 24 + .../arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c | 24 + .../arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c | 24 + .../arm/mve/intrinsics/vqrdmlsdhxq_s16.c | 22 + .../arm/mve/intrinsics/vqrdmlsdhxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c | 22 + .../arm/mve/intrinsics/vqrdmulhq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqrdmulhq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqrdmulhq_m_n_s8.c | 24 + .../arm/mve/intrinsics/vqrdmulhq_m_s16.c | 24 + .../arm/mve/intrinsics/vqrdmulhq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c | 24 + .../{vbicq_m_n_s16.c => vqrshlq_m_n_s16.c} | 10 +- .../{vbicq_m_n_s32.c => vqrshlq_m_n_s32.c} | 10 +- .../{vbicq_m_n_s16.c => vqrshlq_m_n_s8.c} | 14 +- .../{vbicq_m_n_u16.c => vqrshlq_m_n_u16.c} | 10 +- .../{vbicq_m_n_u32.c => vqrshlq_m_n_u32.c} | 10 +- .../{vbicq_m_n_s32.c => vqrshlq_m_n_u8.c} | 14 +- .../gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c | 24 + .../arm/mve/intrinsics/vqrshrnbq_m_n_s16.c | 24 + .../{vbicq_m_n_s16.c => vqrshrnbq_m_n_s32.c} | 11 +- .../arm/mve/intrinsics/vqrshrnbq_m_n_u16.c | 24 + .../{vbicq_m_n_u16.c => vqrshrnbq_m_n_u32.c} | 11 +- .../arm/mve/intrinsics/vqrshrntq_m_n_s16.c | 24 + .../{vbicq_m_n_s16.c => vqrshrntq_m_n_s32.c} | 11 +- .../arm/mve/intrinsics/vqrshrntq_m_n_u16.c | 24 + .../{vbicq_m_n_u16.c => vqrshrntq_m_n_u32.c} | 11 +- .../{vmovnbq_s16.c => vqrshrntq_n_s16.c} | 8 +- .../{vmovnbq_s32.c => vqrshrntq_n_s32.c} | 8 +- .../{vmovnbq_u16.c => vqrshrntq_n_u16.c} | 8 +- .../{vmovnbq_u32.c => vqrshrntq_n_u32.c} | 8 +- .../arm/mve/intrinsics/vqrshrunbq_m_n_s16.c | 24 + .../{vbicq_m_n_u16.c => vqrshrunbq_m_n_s32.c} | 11 +- .../arm/mve/intrinsics/vqrshruntq_m_n_s16.c | 24 + .../{vbicq_m_n_u16.c => vqrshruntq_m_n_s32.c} | 11 +- .../{vqmovunbq_s16.c => vqrshruntq_n_s16.c} | 8 +- .../{vqmovunbq_s32.c => vqrshruntq_n_s32.c} | 8 +- .../{vbicq_m_n_s16.c => vqshlq_m_n_s16.c} | 11 +- .../{vbicq_m_n_s32.c => vqshlq_m_n_s32.c} | 11 +- .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c | 24 + .../{vbicq_m_n_s16.c => vqshlq_m_r_s16.c} | 10 +- .../{vbicq_m_n_s32.c => vqshlq_m_r_s32.c} | 10 +- .../{vbicq_m_n_s16.c => vqshlq_m_r_s8.c} | 14 +- .../{vbicq_m_n_u16.c => vqshlq_m_r_u16.c} | 10 +- .../{vbicq_m_n_u32.c => vqshlq_m_r_u32.c} | 10 +- .../{vbicq_m_n_s32.c => vqshlq_m_r_u8.c} | 14 +- .../gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c | 24 + .../{vbicq_m_n_u16.c => vqshluq_m_n_s16.c} | 10 +- .../{vbicq_m_n_u32.c => vqshluq_m_n_s32.c} | 10 +- .../{vbicq_m_n_s32.c => vqshluq_m_n_s8.c} | 14 +- .../arm/mve/intrinsics/vqshrnbq_m_n_s16.c | 24 + .../{vbicq_m_n_s16.c => vqshrnbq_m_n_s32.c} | 11 +- .../arm/mve/intrinsics/vqshrnbq_m_n_u16.c | 24 + .../{vbicq_m_n_u16.c => vqshrnbq_m_n_u32.c} | 11 +- .../intrinsics/{vmovnbq_s16.c => vqshrnbq_n_s16.c} | 8 +- .../intrinsics/{vmovnbq_s32.c => vqshrnbq_n_s32.c} | 8 +- .../intrinsics/{vmovnbq_u16.c => vqshrnbq_n_u16.c} | 8 +- .../intrinsics/{vmovnbq_u32.c => vqshrnbq_n_u32.c} | 8 +- .../arm/mve/intrinsics/vqshrntq_m_n_s16.c | 24 + .../{vbicq_m_n_s16.c => vqshrntq_m_n_s32.c} | 11 +- .../arm/mve/intrinsics/vqshrntq_m_n_u16.c | 24 + .../{vbicq_m_n_u16.c => vqshrntq_m_n_u32.c} | 11 +- .../intrinsics/{vmovnbq_s16.c => vqshrntq_n_s16.c} | 8 +- .../intrinsics/{vmovnbq_s32.c => vqshrntq_n_s32.c} | 8 +- .../intrinsics/{vmovnbq_u16.c => vqshrntq_n_u16.c} | 8 +- .../intrinsics/{vmovnbq_u32.c => vqshrntq_n_u32.c} | 8 +- .../arm/mve/intrinsics/vqshrunbq_m_n_s16.c | 24 + .../{vbicq_m_n_u16.c => vqshrunbq_m_n_s32.c} | 11 +- .../{vqmovunbq_s16.c => vqshrunbq_n_s16.c} | 8 +- .../{vqmovunbq_s32.c => vqshrunbq_n_s32.c} | 8 +- .../arm/mve/intrinsics/vqshruntq_m_n_s16.c | 24 + .../{vbicq_m_n_u16.c => vqshruntq_m_n_s32.c} | 11 +- .../{vqmovunbq_s16.c => vqshruntq_n_s16.c} | 8 +- .../{vqmovunbq_s32.c => vqshruntq_n_s32.c} | 8 +- .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c | 24 + .../intrinsics/{vbicq_m_n_s16.c => vrev16q_m_s8.c} | 14 +- .../intrinsics/{vbicq_m_n_s32.c => vrev16q_m_u8.c} | 14 +- .../{vcvtq_m_f16_s16.c => vrev32q_m_f16.c} | 10 +- .../{vbicq_m_n_s16.c => vrev32q_m_s16.c} | 10 +- .../intrinsics/{vbicq_m_n_s16.c => vrev32q_m_s8.c} | 14 +- .../{vbicq_m_n_u16.c => vrev32q_m_u16.c} | 10 +- .../intrinsics/{vbicq_m_n_s32.c => vrev32q_m_u8.c} | 14 +- .../{vcvtq_m_f16_s16.c => vrev64q_m_f16.c} | 10 +- .../{vcvtq_m_f32_s32.c => vrev64q_m_f32.c} | 10 +- .../{vbicq_m_n_s16.c => vrev64q_m_s16.c} | 10 +- .../{vbicq_m_n_s32.c => vrev64q_m_s32.c} | 10 +- .../intrinsics/{vbicq_m_n_s16.c => vrev64q_m_s8.c} | 14 +- .../{vbicq_m_n_u16.c => vrev64q_m_u16.c} | 10 +- .../{vbicq_m_n_u32.c => vrev64q_m_u32.c} | 10 +- .../intrinsics/{vbicq_m_n_s32.c => vrev64q_m_u8.c} | 14 +- .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c | 24 + .../arm/mve/intrinsics/vrmlaldavhaq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaq_p_u32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c | 22 + .../{vrmlaldavhaq_s32.c => vrmlaldavhaxq_s32.c} | 8 +- .../arm/mve/intrinsics/vrmlaldavhq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhq_p_u32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhxq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhaq_p_s32.c | 22 + .../{vrmlaldavhaq_s32.c => vrmlsldavhaq_s32.c} | 8 +- .../arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c | 22 + .../{vrmlaldavhaq_s32.c => vrmlsldavhaxq_s32.c} | 8 +- .../arm/mve/intrinsics/vrmlsldavhq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhxq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c | 24 + .../{vcvtq_m_f16_s16.c => vrndaq_m_f16.c} | 10 +- .../{vcvtq_m_f32_s32.c => vrndaq_m_f32.c} | 10 +- .../{vcvtq_m_f16_s16.c => vrndmq_m_f16.c} | 10 +- .../{vcvtq_m_f32_s32.c => vrndmq_m_f32.c} | 10 +- .../{vcvtq_m_f16_s16.c => vrndnq_m_f16.c} | 10 +- .../{vcvtq_m_f32_s32.c => vrndnq_m_f32.c} | 10 +- .../{vcvtq_m_f16_s16.c => vrndpq_m_f16.c} | 10 +- .../{vcvtq_m_f32_s32.c => vrndpq_m_f32.c} | 10 +- .../{vcvtq_m_f16_s16.c => vrndq_m_f16.c} | 10 +- .../{vcvtq_m_f32_s32.c => vrndq_m_f32.c} | 10 +- .../{vcvtq_m_f16_s16.c => vrndxq_m_f16.c} | 10 +- .../{vcvtq_m_f32_s32.c => vrndxq_m_f32.c} | 10 +- .../{vbicq_m_n_s16.c => vrshlq_m_n_s16.c} | 10 +- .../{vbicq_m_n_s32.c => vrshlq_m_n_s32.c} | 10 +- .../{vbicq_m_n_s16.c => vrshlq_m_n_s8.c} | 14 +- .../{vbicq_m_n_u16.c => vrshlq_m_n_u16.c} | 10 +- .../{vbicq_m_n_u32.c => vrshlq_m_n_u32.c} | 10 +- .../{vbicq_m_n_s32.c => vrshlq_m_n_u8.c} | 14 +- .../gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c | 24 + .../arm/mve/intrinsics/vrshrnbq_m_n_s16.c | 24 + .../{vbicq_m_n_s16.c => vrshrnbq_m_n_s32.c} | 11 +- .../arm/mve/intrinsics/vrshrnbq_m_n_u16.c | 24 + .../{vbicq_m_n_u16.c => vrshrnbq_m_n_u32.c} | 11 +- .../intrinsics/{vmovnbq_s16.c => vrshrnbq_n_s16.c} | 8 +- .../intrinsics/{vmovnbq_s32.c => vrshrnbq_n_s32.c} | 8 +- .../intrinsics/{vmovnbq_u16.c => vrshrnbq_n_u16.c} | 8 +- .../intrinsics/{vmovnbq_u32.c => vrshrnbq_n_u32.c} | 8 +- .../arm/mve/intrinsics/vrshrntq_m_n_s16.c | 24 + .../{vbicq_m_n_s16.c => vrshrntq_m_n_s32.c} | 11 +- .../arm/mve/intrinsics/vrshrntq_m_n_u16.c | 24 + .../{vbicq_m_n_u16.c => vrshrntq_m_n_u32.c} | 11 +- .../intrinsics/{vmovnbq_s16.c => vrshrntq_n_s16.c} | 8 +- .../intrinsics/{vmovnbq_s32.c => vrshrntq_n_s32.c} | 8 +- .../intrinsics/{vmovnbq_u16.c => vrshrntq_n_u16.c} | 8 +- .../intrinsics/{vmovnbq_u32.c => vrshrntq_n_u32.c} | 8 +- .../{vbicq_m_n_s16.c => vrshrq_m_n_s16.c} | 11 +- .../{vbicq_m_n_s32.c => vrshrq_m_n_s32.c} | 11 +- .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c | 24 + .../arm/mve/intrinsics/vshllbq_m_n_s16.c | 24 + .../{vbicq_m_n_s16.c => vshllbq_m_n_s8.c} | 11 +- .../arm/mve/intrinsics/vshllbq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c | 24 + .../arm/mve/intrinsics/vshlltq_m_n_s16.c | 24 + .../{vbicq_m_n_s16.c => vshlltq_m_n_s8.c} | 11 +- .../arm/mve/intrinsics/vshlltq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c | 24 + .../{vbicq_m_n_s16.c => vshlq_m_n_s16.c} | 11 +- .../{vbicq_m_n_s32.c => vshlq_m_n_s32.c} | 11 +- .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c | 24 + .../{vbicq_m_n_u16.c => vshlq_m_n_u16.c} | 11 +- .../{vbicq_m_n_u32.c => vshlq_m_n_u32.c} | 11 +- .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c | 24 + .../{vbicq_m_n_s16.c => vshlq_m_r_s16.c} | 10 +- .../{vbicq_m_n_s32.c => vshlq_m_r_s32.c} | 10 +- .../intrinsics/{vbicq_m_n_s16.c => vshlq_m_r_s8.c} | 14 +- .../{vbicq_m_n_u16.c => vshlq_m_r_u16.c} | 10 +- .../{vbicq_m_n_u32.c => vshlq_m_r_u32.c} | 10 +- .../intrinsics/{vbicq_m_n_s32.c => vshlq_m_r_u8.c} | 14 +- .../intrinsics/{vbicq_m_n_s16.c => vshlq_m_s16.c} | 10 +- .../intrinsics/{vbicq_m_n_s32.c => vshlq_m_s32.c} | 10 +- .../gcc.target/arm/mve/intrinsics/vshlq_m_s8.c | 23 + .../intrinsics/{vbicq_m_n_u16.c => vshlq_m_u16.c} | 10 +- .../intrinsics/{vbicq_m_n_u32.c => vshlq_m_u32.c} | 10 +- .../gcc.target/arm/mve/intrinsics/vshlq_m_u8.c | 23 + .../arm/mve/intrinsics/vshrnbq_m_n_s16.c | 24 + .../{vbicq_m_n_s16.c => vshrnbq_m_n_s32.c} | 11 +- .../arm/mve/intrinsics/vshrnbq_m_n_u16.c | 24 + .../{vbicq_m_n_u16.c => vshrnbq_m_n_u32.c} | 11 +- .../intrinsics/{vmovnbq_s16.c => vshrnbq_n_s16.c} | 8 +- .../intrinsics/{vmovnbq_s32.c => vshrnbq_n_s32.c} | 8 +- .../intrinsics/{vmovnbq_u16.c => vshrnbq_n_u16.c} | 8 +- .../intrinsics/{vmovnbq_u32.c => vshrnbq_n_u32.c} | 8 +- .../arm/mve/intrinsics/vshrntq_m_n_s16.c | 24 + .../{vbicq_m_n_s16.c => vshrntq_m_n_s32.c} | 11 +- .../arm/mve/intrinsics/vshrntq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vshrntq_m_n_u32.c | 23 + .../intrinsics/{vmovnbq_s16.c => vshrntq_n_s16.c} | 8 +- .../intrinsics/{vmovnbq_s32.c => vshrntq_n_s32.c} | 8 +- .../intrinsics/{vmovnbq_u16.c => vshrntq_n_u16.c} | 8 +- .../intrinsics/{vmovnbq_u32.c => vshrntq_n_u32.c} | 8 +- .../{vbicq_m_n_s16.c => vshrq_m_n_s16.c} | 11 +- .../{vbicq_m_n_s32.c => vshrq_m_n_s32.c} | 11 +- .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c | 24 + .../{vbicq_m_n_u16.c => vshrq_m_n_u16.c} | 11 +- .../{vbicq_m_n_u32.c => vshrq_m_n_u32.c} | 11 +- .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c | 24 + .../{vbicq_m_n_s16.c => vsliq_m_n_s16.c} | 11 +- .../{vbicq_m_n_s32.c => vsliq_m_n_s32.c} | 11 +- .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c | 24 + .../{vbicq_m_n_u16.c => vsliq_m_n_u16.c} | 11 +- .../{vbicq_m_n_u32.c => vsliq_m_n_u32.c} | 11 +- .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c | 24 + .../mve/intrinsics/{veorq_s16.c => vsliq_n_s16.c} | 8 +- .../mve/intrinsics/{veorq_s32.c => vsliq_n_s32.c} | 8 +- .../mve/intrinsics/{vbicq_s8.c => vsliq_n_s8.c} | 8 +- .../mve/intrinsics/{veorq_u16.c => vsliq_n_u16.c} | 8 +- .../mve/intrinsics/{vabdq_u32.c => vsliq_n_u32.c} | 8 +- .../mve/intrinsics/{vabdq_u8.c => vsliq_n_u8.c} | 8 +- .../{vbicq_m_n_s16.c => vsriq_m_n_s16.c} | 10 +- .../{vbicq_m_n_s32.c => vsriq_m_n_s32.c} | 10 +- .../intrinsics/{vbicq_m_n_s16.c => vsriq_m_n_s8.c} | 14 +- .../{vbicq_m_n_u16.c => vsriq_m_n_u16.c} | 10 +- .../{vbicq_m_n_u32.c => vsriq_m_n_u32.c} | 10 +- .../intrinsics/{vbicq_m_n_s32.c => vsriq_m_n_u8.c} | 14 +- .../mve/intrinsics/{veorq_s16.c => vsriq_n_s16.c} | 8 +- .../mve/intrinsics/{veorq_s32.c => vsriq_n_s32.c} | 8 +- .../mve/intrinsics/{vbicq_s8.c => vsriq_n_s8.c} | 8 +- .../mve/intrinsics/{vabdq_u16.c => vsriq_n_u16.c} | 8 +- .../mve/intrinsics/{vabdq_u32.c => vsriq_n_u32.c} | 8 +- .../mve/intrinsics/{vabdq_u8.c => vsriq_n_u8.c} | 8 +- .../gcc.target/arm/mve/intrinsics/vst1q_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_s8.c | 22 + .../mve/intrinsics/vstrbq_scatter_offset_p_s16.c | 22 + .../mve/intrinsics/vstrbq_scatter_offset_p_s32.c | 22 + .../mve/intrinsics/vstrbq_scatter_offset_p_s8.c | 22 + .../mve/intrinsics/vstrbq_scatter_offset_p_u16.c | 22 + .../mve/intrinsics/vstrbq_scatter_offset_p_u32.c | 22 + .../mve/intrinsics/vstrbq_scatter_offset_p_u8.c | 22 + .../arm/mve/intrinsics/vstrbq_scatter_offset_s16.c | 22 + .../arm/mve/intrinsics/vstrbq_scatter_offset_s32.c | 22 + .../arm/mve/intrinsics/vstrbq_scatter_offset_s8.c | 22 + .../arm/mve/intrinsics/vstrbq_scatter_offset_u16.c | 22 + .../arm/mve/intrinsics/vstrbq_scatter_offset_u32.c | 22 + .../arm/mve/intrinsics/vstrbq_scatter_offset_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_u8.c | 22 + .../arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c | 22 + .../arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c | 22 + .../arm/mve/intrinsics/vstrdq_scatter_base_s64.c | 22 + .../arm/mve/intrinsics/vstrdq_scatter_base_u64.c | 22 + .../mve/intrinsics/vstrdq_scatter_offset_p_s64.c | 22 + .../mve/intrinsics/vstrdq_scatter_offset_p_u64.c | 22 + .../arm/mve/intrinsics/vstrdq_scatter_offset_s64.c | 22 + .../arm/mve/intrinsics/vstrdq_scatter_offset_u64.c | 22 + .../vstrdq_scatter_shifted_offset_p_s64.c | 22 + .../vstrdq_scatter_shifted_offset_p_u64.c | 22 + .../intrinsics/vstrdq_scatter_shifted_offset_s64.c | 22 + .../intrinsics/vstrdq_scatter_shifted_offset_u64.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_s32.c | 22 + .../arm/mve/intrinsics/vstrhq_scatter_offset_f16.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_f16.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_s16.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_s32.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_u16.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_u32.c | 22 + .../arm/mve/intrinsics/vstrhq_scatter_offset_s16.c | 22 + .../arm/mve/intrinsics/vstrhq_scatter_offset_s32.c | 22 + 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.../gcc.target/arm/mve/intrinsics/vsubq_m_u8.c | 23 + gcc/tree-ssa-dom.c | 9 +- gcc/tree-ssa-forwprop.c | 11 +- gcc/tree-ssa-loop-im.c | 3 +- gcc/tree-ssa-strlen.c | 5 +- gcc/tree-ssa-strlen.h | 2 +- libgomp/ChangeLog | 12 + .../libgomp.oacc-c++/firstprivate-mappings-1.C | 9 + .../firstprivate-mappings-1.c | 9 + .../libgomp.oacc-fortran/atomic_capture-1.f90 | 30 +- libstdc++-v3/ChangeLog | 33 + libstdc++-v3/include/bits/stl_algobase.h | 2 +- libstdc++-v3/include/bits/stream_iterator.h | 4 +- libstdc++-v3/include/bits/streambuf_iterator.h | 4 +- libstdc++-v3/include/experimental/executor | 226 +- libstdc++-v3/include/experimental/socket | 18 +- libstdc++-v3/include/std/stop_token | 12 + .../testsuite/experimental/net/executor/1.cc | 93 + 1228 files changed, 47364 insertions(+), 5802 deletions(-) create mode 100644 gcc/testsuite/g++.dg/abi/lambda-vis.C create mode 100644 gcc/testsuite/g++.dg/abi/mangle74.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/enum40.C create mode 100644 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100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f16_s16.c => vabsq_m_f16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f32_s32.c => vabsq_m_f32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vabsq_m_s16.c} (56%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vabsq_m_s32.c} (56%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vabsq_m_s8.c} (52%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c create mode 100644 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mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vclsq_m_s16.c} (56%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vclsq_m_s32.c} (56%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vclsq_m_s8.c} (52%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vclzq_m_s16.c} (56%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vclzq_m_s32.c} (56%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vclzq_m_s8.c} (52%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vclzq_m_u16.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vclzq_m_u32.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vclzq_m_u8.c} (52%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f16_s16.c => vcmlaq_m_f1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f32_s32.c => vcmlaq_m_f3 [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpcsq_m_n_u16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpcsq_m_n_u32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpcsq_m_n_u8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpcsq_m_u16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpcsq_m_u32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpcsq_m_u8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f16.c => vcmpeqq_m_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f32.c => vcmpeqq_m_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpeqq_m_n_s16.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpeqq_m_n_s32.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpeqq_m_n_s8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpeqq_m_n_u16.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpeqq_m_n_u32.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpeqq_m_n_u8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpeqq_m_s16.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpeqq_m_s32.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpeqq_m_s8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpeqq_m_u16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpeqq_m_u32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpeqq_m_u8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f16.c => vcmpgeq_m_f16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f32.c => vcmpgeq_m_f32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f16.c => vcmpgeq_m_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f32.c => vcmpgeq_m_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpgeq_m_n_s16.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpgeq_m_n_s32.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpgeq_m_n_s8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpgeq_m_s16.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpgeq_m_s32.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpgeq_m_s8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f16.c => vcmpgtq_m_f16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f32.c => vcmpgtq_m_f32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f16.c => vcmpgtq_m_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f32.c => vcmpgtq_m_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpgtq_m_n_s16.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpgtq_m_n_s32.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpgtq_m_n_s8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpgtq_m_s16.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpgtq_m_s32.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpgtq_m_s8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmphiq_m_n_u16.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmphiq_m_n_u32.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmphiq_m_n_u8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmphiq_m_u16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmphiq_m_u32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmphiq_m_u8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f16.c => vcmpleq_m_f16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f32.c => vcmpleq_m_f32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f16.c => vcmpleq_m_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f32.c => vcmpleq_m_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpleq_m_n_s16.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpleq_m_n_s32.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpleq_m_n_s8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpleq_m_s16.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpleq_m_s32.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpleq_m_s8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f16.c => vcmpltq_m_f16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f32.c => vcmpltq_m_f32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f16.c => vcmpltq_m_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f32.c => vcmpltq_m_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpltq_m_n_s16.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpltq_m_n_s32.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpltq_m_n_s8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpltq_m_s16.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpltq_m_s32.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpltq_m_s8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f16.c => vcmpneq_m_f16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f32.c => vcmpneq_m_f32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f16.c => vcmpneq_m_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f32.c => vcmpneq_m_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpneq_m_n_s16.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpneq_m_n_s32.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpneq_m_n_s8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpneq_m_n_u16.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpneq_m_n_u32.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpneq_m_n_u8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpneq_m_s16.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpneq_m_s32.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpneq_m_s8.c} (59%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpneq_m_u16.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpneq_m_u32.c} (58%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp16q_m.c => vcmpneq_m_u8.c} (59%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f16_s16.c => vcvtbq_m_f1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f32_s32.c => vcvtbq_m_f3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtaq_m_s16_f16.c => vcvtmq_m_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtaq_m_s32_f32.c => vcvtmq_m_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtaq_m_u16_f16.c => vcvtmq_m_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtaq_m_u32_f32.c => vcvtmq_m_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtaq_m_s16_f16.c => vcvtnq_m_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtaq_m_s32_f32.c => vcvtnq_m_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtaq_m_u16_f16.c => vcvtnq_m_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtaq_m_u32_f32.c => vcvtnq_m_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtaq_m_s16_f16.c => vcvtpq_m_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtaq_m_s32_f32.c => vcvtpq_m_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtaq_m_u16_f16.c => vcvtpq_m_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtaq_m_u32_f32.c => vcvtpq_m_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f16_s16.c => vcvtq_m_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f16_u16.c => vcvtq_m_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f32_s32.c => vcvtq_m_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f32_u32.c => vcvtq_m_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtaq_m_s16_f16.c => vcvtq_m_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtaq_m_s32_f32.c => vcvtq_m_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtaq_m_u16_f16.c => vcvtq_m_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtaq_m_u32_f32.c => vcvtq_m_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtaq_m_s16_f16.c => vcvtq_m_s1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtaq_m_s32_f32.c => vcvtq_m_s3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtaq_m_u16_f16.c => vcvtq_m_u1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtaq_m_u32_f32.c => vcvtq_m_u3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f16_s16.c => vcvttq_m_f1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f32_s32.c => vcvttq_m_f3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f16_s16.c => vdupq_m_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f32_s32.c => vdupq_m_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vdupq_m_n_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vdupq_m_n_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vdupq_m_n_s8. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vdupq_m_n_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vdupq_m_n_u32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vdupq_m_n_u8. [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f16_s16.c => vfmaq_m_f16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f32_s32.c => vfmaq_m_f32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f16_s16.c => vfmaq_m_n_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f32_s32.c => vfmaq_m_n_f [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f16_s16.c => vfmasq_m_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f32_s32.c => vfmasq_m_n_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f16_s16.c => vfmsq_m_f16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f32_s32.c => vfmsq_m_f32 [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_n_f16_s16.c => vld1q_f16.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_n_f32_s32.c => vld1q_f32.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vandq_s16.c => vld1q_s16.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vandq_s32.c => vld1q_s32.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabsq_s8.c => vld1q_s8.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_u16.c => vld1q_u16.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_u32.c => vld1q_u32.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_u8.c => vld1q_u8.c} (50%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offse [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_s16.c => vldrbq_s16.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_s32.c => vldrbq_s32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_s8.c => vldrbq_s8.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_u16.c => vldrbq_u16.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_u32.c => vldrbq_u32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_u8.c => vldrbq_u8.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_s16.c => vldrbq_z_s16.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_s32.c => vldrbq_z_s32.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_s8.c => vldrbq_z_s8.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_u16.c => vldrbq_z_u16.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_u32.c => vldrbq_z_u32.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_u8.c => vldrbq_z_u8.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_s16.c => vldrdq_gather_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_u16.c => vldrdq_gather_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_s16.c => vldrdq_gather_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_u16.c => vldrdq_gather_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shift [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_f16_u16.c => vldrhq_f16.c} (65%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_s16.c => vldrhq_s16.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_s32.c => vldrhq_s32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_u16.c => vldrhq_u16.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_u32.c => vldrhq_u32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtbq_f16_f32.c => vldrhq_z_f16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_s16.c => vldrhq_z_s16.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_s32.c => vldrhq_z_s32.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_u16.c => vldrhq_z_u16.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_u32.c => vldrhq_z_u32.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_f32.c => vldrwq_f32.c} (65%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_f32.c => vldrwq_gather_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_s32.c => vldrwq_gather_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_u32.c => vldrwq_gather_b [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_f32.c => vldrwq_gather_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_s32.c => vldrwq_gather_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_u32.c => vldrwq_gather_b [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shift [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_s32.c => vldrwq_s32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_u32.c => vldrwq_u32.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_f32.c => vldrwq_z_f32.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcreateq_s32.c => vldrwq_z_s32.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_u32.c => vldrwq_z_u32.c} (60%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vmaxaq_m_s16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vmaxaq_m_s32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vmaxaq_m_s8.c} (54%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f16.c => vmaxnmaq_m_f1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f32.c => vmaxnmaq_m_f3 [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vminaq_m_s16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vminaq_m_s32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vminaq_m_s8.c} (54%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f16.c => vminnmaq_m_f1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f32.c => vminnmaq_m_f3 [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabavq_u16.c => vmladavaq_u16.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabavq_u32.c => vmladavaq_u32.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabavq_u8.c => vmladavaq_u8.c} (63%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrmlaldavhaq_s32.c => vmlaldavaq [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrmlaldavhaq_u32.c => vmlaldavaq [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrmlaldavhaq_s32.c => vmlaldavax [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vmlaq_m_n_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vmlaq_m_n_s32 [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vmlaq_m_n_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vmlaq_m_n_u32 [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vmlasq_m_n_s1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vmlasq_m_n_s3 [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vmlasq_m_n_u1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vmlasq_m_n_u3 [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrmlaldavhaq_s32.c => vmlsldavaq [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrmlaldavhaq_s32.c => vmlsldavax [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vmovlbq_m_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vmovlbq_m_s8. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vmovlbq_m_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vmovlbq_m_u8. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vmovltq_m_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vmovltq_m_s8. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vmovltq_m_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vmovltq_m_u8. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vmovnbq_m_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vmovnbq_m_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vmovnbq_m_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vmovnbq_m_u32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vmovntq_m_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vmovntq_m_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vmovntq_m_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vmovntq_m_u32 [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vmvnq_m_n_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vmvnq_m_n_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vmvnq_m_n_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vmvnq_m_n_u32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vmvnq_m_s16.c} (56%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vmvnq_m_s32.c} (56%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vmvnq_m_s8.c} (52%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vmvnq_m_u16.c} (56%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vmvnq_m_u32.c} (56%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vmvnq_m_u8.c} (52%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f16_s16.c => vnegq_m_f16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f32_s32.c => vnegq_m_f32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vnegq_m_s16.c} (56%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vnegq_m_s32.c} (56%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vnegq_m_s8.c} (52%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vorrq_m_n_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vorrq_m_n_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vorrq_m_n_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vorrq_m_n_u32 [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f16.c => vpselq_f16.c} (56%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcmpeqq_m_f32.c => vpselq_f32.c} (56%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vqabsq_m_s16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vqabsq_m_s32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vqabsq_m_s8.c} (52%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vqdmlahq_m_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vqdmlahq_m_n_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vqmovnbq_m_s1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vqmovnbq_m_s3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vqmovnbq_m_u1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vqmovnbq_m_u3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vqmovntq_m_s1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vqmovntq_m_s3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vqmovntq_m_u1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vqmovntq_m_u3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vqmovunbq_m_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vqmovunbq_m_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vqmovuntq_m_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vqmovuntq_m_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vqnegq_m_s16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vqnegq_m_s32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vqnegq_m_s8.c} (52%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vqrshlq_m_n_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vqrshlq_m_n_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vqrshlq_m_n_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vqrshlq_m_n_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vqrshlq_m_n_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vqrshlq_m_n_u [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vqrshrnbq_m_n [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vqrshrnbq_m_n [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vqrshrntq_m_n [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vqrshrntq_m_n [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_s16.c => vqrshrntq_n_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_s32.c => vqrshrntq_n_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_u16.c => vqrshrntq_n_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_u32.c => vqrshrntq_n_u32 [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vqrshrunbq_m_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vqrshruntq_m_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vqmovunbq_s16.c => vqrshruntq_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vqmovunbq_s32.c => vqrshruntq_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vqshlq_m_n_s1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vqshlq_m_n_s3 [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vqshlq_m_r_s1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vqshlq_m_r_s3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vqshlq_m_r_s8 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vqshlq_m_r_u1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vqshlq_m_r_u3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vqshlq_m_r_u8 [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vqshluq_m_n_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vqshluq_m_n_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vqshluq_m_n_s [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vqshrnbq_m_n_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vqshrnbq_m_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_s16.c => vqshrnbq_n_s16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_s32.c => vqshrnbq_n_s32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_u16.c => vqshrnbq_n_u16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_u32.c => vqshrnbq_n_u32. [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vqshrntq_m_n_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vqshrntq_m_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_s16.c => vqshrntq_n_s16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_s32.c => vqshrntq_n_s32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_u16.c => vqshrntq_n_u16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_u32.c => vqshrntq_n_u32. [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vqshrunbq_m_n [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vqmovunbq_s16.c => vqshrunbq_n_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vqmovunbq_s32.c => vqshrunbq_n_s [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vqshruntq_m_n [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vqmovunbq_s16.c => vqshruntq_n_s [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vqmovunbq_s32.c => vqshruntq_n_s [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vrev16q_m_s8. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vrev16q_m_u8. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f16_s16.c => vrev32q_m_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vrev32q_m_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vrev32q_m_s8. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vrev32q_m_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vrev32q_m_u8. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f16_s16.c => vrev64q_m_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f32_s32.c => vrev64q_m_f [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vrev64q_m_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vrev64q_m_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vrev64q_m_s8. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vrev64q_m_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vrev64q_m_u32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vrev64q_m_u8. [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrmlaldavhaq_s32.c => vrmlaldavh [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrmlaldavhaq_s32.c => vrmlsldavh [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vrmlaldavhaq_s32.c => vrmlsldavh [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f16_s16.c => vrndaq_m_f1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f32_s32.c => vrndaq_m_f3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f16_s16.c => vrndmq_m_f1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f32_s32.c => vrndmq_m_f3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f16_s16.c => vrndnq_m_f1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f32_s32.c => vrndnq_m_f3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f16_s16.c => vrndpq_m_f1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f32_s32.c => vrndpq_m_f3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f16_s16.c => vrndq_m_f16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f32_s32.c => vrndq_m_f32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f16_s16.c => vrndxq_m_f1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vcvtq_m_f32_s32.c => vrndxq_m_f3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vrshlq_m_n_s1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vrshlq_m_n_s3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vrshlq_m_n_s8 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vrshlq_m_n_u1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vrshlq_m_n_u3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vrshlq_m_n_u8 [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vrshrnbq_m_n_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vrshrnbq_m_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_s16.c => vrshrnbq_n_s16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_s32.c => vrshrnbq_n_s32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_u16.c => vrshrnbq_n_u16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_u32.c => vrshrnbq_n_u32. [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vrshrntq_m_n_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vrshrntq_m_n_ [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_s16.c => vrshrntq_n_s16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_s32.c => vrshrntq_n_s32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_u16.c => vrshrntq_n_u16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_u32.c => vrshrntq_n_u32. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vrshrq_m_n_s1 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vrshrq_m_n_s3 [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vshllbq_m_n_s [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vshlltq_m_n_s [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vshlq_m_n_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vshlq_m_n_s32 [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vshlq_m_n_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vshlq_m_n_u32 [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vshlq_m_r_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vshlq_m_r_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vshlq_m_r_s8. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vshlq_m_r_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vshlq_m_r_u32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vshlq_m_r_u8. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vshlq_m_s16.c} (52%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vshlq_m_s32.c} (52%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vshlq_m_u16.c} (52%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vshlq_m_u32.c} (52%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vshrnbq_m_n_s [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vshrnbq_m_n_u [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_s16.c => vshrnbq_n_s16.c} (61%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_s32.c => vshrnbq_n_s32.c} (61%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_u16.c => vshrnbq_n_u16.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_u32.c => vshrnbq_n_u32.c} (62%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vshrntq_m_n_s [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_s16.c => vshrntq_n_s16.c} (61%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_s32.c => vshrntq_n_s32.c} (61%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_u16.c => vshrntq_n_u16.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovnbq_u32.c => vshrntq_n_u32.c} (62%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vshrq_m_n_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vshrq_m_n_s32 [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vshrq_m_n_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vshrq_m_n_u32 [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vsliq_m_n_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vsliq_m_n_s32 [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vsliq_m_n_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vsliq_m_n_u32 [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{veorq_s16.c => vsliq_n_s16.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{veorq_s32.c => vsliq_n_s32.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_s8.c => vsliq_n_s8.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{veorq_u16.c => vsliq_n_u16.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_u32.c => vsliq_n_u32.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_u8.c => vsliq_n_u8.c} (64%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vsriq_m_n_s16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vsriq_m_n_s32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vsriq_m_n_s8. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vsriq_m_n_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vsriq_m_n_u32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vsriq_m_n_u8. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{veorq_s16.c => vsriq_n_s16.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{veorq_s32.c => vsriq_n_s32.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_s8.c => vsriq_n_s8.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_u16.c => vsriq_n_u16.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_u32.c => vsriq_n_u32.c} (63%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_u8.c => vsriq_n_u8.c} (64%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s16.c => vsubq_m_s16.c} (52%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_s32.c => vsubq_m_s32.c} (52%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u16.c => vsubq_m_u16.c} (52%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_m_n_u32.c => vsubq_m_u32.c} (52%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c create mode 100644 libstdc++-v3/testsuite/experimental/net/executor/1.cc