This is an automated email from the git hooks/post-receive script.
tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_check/master-arm in repository toolchain/ci/gcc.
from 7e71909af2c x86: Speed up target attribute handling by using a cache adds 97ffef35532 testsuite: Fix up pr103456.c testcase [PR103456] adds f7854b90897 Add TARGET_IFUNC_REF_LOCAL_OK adds 06f2e7d49fc sve: combine nested if predicates adds add31efdc7b RISC-V: Add option defines for Scalar Cryptography adds 0962bff477a RISC-V: Add implied defines of Zk, Zkn and Zks
No new revisions were added by this update.
Summary of changes: gcc/common/config/riscv/riscv-common.c | 38 +++++++++++- gcc/config/i386/i386-expand.c | 2 +- gcc/config/i386/i386-protos.h | 1 + gcc/config/i386/i386.c | 25 +++++++- gcc/config/riscv/arch-canonicalize | 16 ++++- gcc/config/riscv/riscv-opts.h | 22 +++++++ gcc/config/riscv/riscv.opt | 3 + gcc/doc/tm.texi | 5 ++ gcc/doc/tm.texi.in | 2 + gcc/target.def | 8 +++ gcc/testsuite/gcc.dg/ubsan/pr103456.c | 2 +- .../gcc.target/aarch64/sve/pred-combine-and.c | 18 ++++++ gcc/testsuite/gcc.target/i386/pr83782-1.c | 26 ++++++++ gcc/testsuite/gcc.target/i386/pr83782-2.c | 26 ++++++++ gcc/tree-vect-stmts.c | 70 +++++++++++++++++----- gcc/tree-vectorizer.h | 9 +++ gcc/varasm.c | 3 +- 17 files changed, 255 insertions(+), 21 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pred-combine-and.c create mode 100644 gcc/testsuite/gcc.target/i386/pr83782-1.c create mode 100644 gcc/testsuite/gcc.target/i386/pr83782-2.c