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from ee117887838 Daily bump. new c129d22de6b RISC-V: Fix VSETVL PASS bug in exception handling new d7f8c79a57e RISC-V: Add unary C/C++ API support new 2855e295484 RISC-V: Add vnot.v C API tests new 340a770d9dc RISC-V: Add vneg.v C/C++ API tests new 779e441103e RISC-V: Add unary constraint tests. new 4170a0f021f RISC-V: Add vnot.v C++ API tests new eeb50b70354 RISC-V: Add vneg.v C++ API tests new 7ad729a0df0 RISC-V: Add saturating Addition && Subtraction C/C++ Support new b2691c96efd RISC-V: Add saturating Add && Sub vx constraint tests new 098e7fc10e4 RISC-V: Add vsadd.vv C++ API tests new 77c9ee5e22e RISC-V: Add vsaddu.vv C++ API tests. new cc01b5c0659 RISC-V: Add vsub.vv C++ API tests new ae9b600f2d5 RISC-V: Add vssubu.vv C++ API tests new cd92bd48c55 RISC-V: Add vssubu.vv C API tests new bd182ae41bc RISC-V: Add vssub.vv C API tests new e5600572a17 RISC-V: Add vsaddu.vv C API tests new 6a04629d5a0 RISC-V: Add vsadd.vv C API tests new d6c18465cbb RISC-V: Add vssubu.vx C API tests new 1b7f3e20a2f RISC-V: Add vssub.vx C API tests new ed0c99027d4 RISC-V: Add vsaddu.vx C++ API tests new 933dce55100 RISC-V: Add vsadd.vx C++ API tests new e5dd529dcdb RISC-V: Add vssubu.vx C++ API tests new 3762ff2450c RISC-V: Add vssub.vx C++ API tests new a1ca758fd5e RISC-V: Add vsaddu.vx overloaded API tests new 064a2d53a38 RISC-V: Add vsadd.vx C++ overloaded API tests
The 25 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: gcc/config/riscv/iterators.md | 16 +- gcc/config/riscv/riscv-v.cc | 5 +- gcc/config/riscv/riscv-vector-builtins-bases.cc | 23 ++ gcc/config/riscv/riscv-vector-builtins-bases.h | 6 + .../riscv/riscv-vector-builtins-functions.def | 81 +++--- gcc/config/riscv/riscv-vector-builtins-shapes.cc | 6 +- gcc/config/riscv/riscv-vector-builtins-shapes.h | 2 +- gcc/config/riscv/riscv-vector-builtins.cc | 12 + gcc/config/riscv/riscv-vsetvl.cc | 10 +- gcc/config/riscv/vector-iterators.md | 54 +++- gcc/config/riscv/vector.md | 280 +++++++++++++++++- .../g++.target/riscv/rvv/base/exception-1.C | 27 ++ gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-1.C | 314 +++++++++++++++++++++ gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-2.C | 314 +++++++++++++++++++++ gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vneg_v_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vneg_v_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vneg_v_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vneg_v_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vneg_v_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vneg_v_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vneg_v_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vneg_v_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vneg_v_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vneg_v_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vneg_v_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vneg_v_tumu-3.C | 160 +++++++++++ gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-1.C | 314 +++++++++++++++++++++ gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-2.C | 314 +++++++++++++++++++++ gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vnot_v_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vnot_v_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vnot_v_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vnot_v_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vnot_v_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vnot_v_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vnot_v_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vnot_v_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vnot_v_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vnot_v_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vnot_v_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vnot_v_tumu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsadd_vv-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsadd_vv-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsadd_vv-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsadd_vv_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsadd_vv_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsadd_vv_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsadd_vv_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsadd_vv_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsadd_vv_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsadd_vv_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsadd_vv_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsadd_vv_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsadd_vv_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsadd_vv_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsadd_vv_tumu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsadd_vx_mu_rv32-1.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vsadd_vx_mu_rv32-2.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vsadd_vx_mu_rv32-3.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vsadd_vx_mu_rv64-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsadd_vx_mu_rv64-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsadd_vx_mu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsadd_vx_rv32-1.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsadd_vx_rv32-2.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsadd_vx_rv32-3.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsadd_vx_rv64-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsadd_vx_rv64-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsadd_vx_rv64-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsadd_vx_tu_rv32-1.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vsadd_vx_tu_rv32-2.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vsadd_vx_tu_rv32-3.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vsadd_vx_tu_rv64-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsadd_vx_tu_rv64-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsadd_vx_tu_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vsadd_vx_tum_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vsadd_vx_tum_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vsadd_vx_tum_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vsadd_vx_tum_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vsadd_vx_tum_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vsadd_vx_tum_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vsadd_vx_tumu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vsadd_vx_tumu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vsadd_vx_tumu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vsadd_vx_tumu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vsadd_vx_tumu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vsadd_vx_tumu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vv_tumu-3.C | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_mu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_mu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_mu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_mu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_mu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_mu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vx_rv32-1.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vx_rv32-2.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vx_rv32-3.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vx_rv64-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vx_rv64-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vsaddu_vx_rv64-3.C | 314 +++++++++++++++++++++ .../riscv/rvv/base/vsaddu_vx_tu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tu_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tum_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tum_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tum_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tum_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tum_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tum_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tumu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tumu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tumu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tumu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tumu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tumu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vv-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssub_vv-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssub_vv-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssub_vv_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vv_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vv_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vv_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vv_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vv_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vv_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vv_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vv_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vv_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vv_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vv_tumu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_mu_rv32-1.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_mu_rv32-2.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_mu_rv32-3.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_mu_rv64-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_mu_rv64-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_mu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_rv32-1.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_rv32-2.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_rv32-3.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_rv64-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_rv64-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_rv64-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_tu_rv32-1.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_tu_rv32-2.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_tu_rv32-3.C | 157 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_tu_rv64-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_tu_rv64-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssub_vx_tu_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vssub_vx_tum_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vssub_vx_tum_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vssub_vx_tum_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vssub_vx_tum_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vssub_vx_tum_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vssub_vx_tum_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vssub_vx_tumu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vssub_vx_tumu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vssub_vx_tumu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vssub_vx_tumu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vssub_vx_tumu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vssub_vx_tumu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv-3.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv_mu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv_mu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv_mu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv_tu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv_tu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv_tu-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv_tum-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv_tum-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv_tum-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv_tumu-1.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv_tumu-2.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssubu_vv_tumu-3.C | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_mu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_mu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_mu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_mu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_mu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_mu_rv64-3.C | 160 +++++++++++ .../g++.target/riscv/rvv/base/vssubu_vx_rv32-1.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssubu_vx_rv32-2.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssubu_vx_rv32-3.C | 308 ++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssubu_vx_rv64-1.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssubu_vx_rv64-2.C | 314 +++++++++++++++++++++ .../g++.target/riscv/rvv/base/vssubu_vx_rv64-3.C | 314 +++++++++++++++++++++ .../riscv/rvv/base/vssubu_vx_tu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tu_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tum_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tum_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tum_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tum_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tum_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tum_rv64-3.C | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tumu_rv32-1.C | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tumu_rv32-2.C | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tumu_rv32-3.C | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tumu_rv64-1.C | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tumu_rv64-2.C | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tumu_rv64-3.C | 160 +++++++++++ ...x_constraint-94.c => binop_vx_constraint-100.c} | 6 +- ...x_constraint-49.c => binop_vx_constraint-101.c} | 6 +- ...x_constraint-90.c => binop_vx_constraint-102.c} | 6 +- .../riscv/rvv/base/binop_vx_constraint-103.c | 123 ++++++++ .../riscv/rvv/base/binop_vx_constraint-104.c | 72 +++++ ...x_constraint-81.c => binop_vx_constraint-105.c} | 8 +- ...x_constraint-81.c => binop_vx_constraint-106.c} | 8 +- ...x_constraint-83.c => binop_vx_constraint-107.c} | 8 +- ...x_constraint-84.c => binop_vx_constraint-108.c} | 8 +- ...x_constraint-91.c => binop_vx_constraint-109.c} | 56 ++-- ...x_constraint-64.c => binop_vx_constraint-110.c} | 32 +-- ...x_constraint-93.c => binop_vx_constraint-111.c} | 6 +- ...x_constraint-94.c => binop_vx_constraint-112.c} | 6 +- ...x_constraint-49.c => binop_vx_constraint-113.c} | 6 +- ...x_constraint-90.c => binop_vx_constraint-114.c} | 6 +- ...x_constraint-80.c => binop_vx_constraint-115.c} | 32 +-- ...x_constraint-81.c => binop_vx_constraint-116.c} | 6 +- ...x_constraint-81.c => binop_vx_constraint-117.c} | 6 +- ...x_constraint-83.c => binop_vx_constraint-118.c} | 6 +- ...x_constraint-84.c => binop_vx_constraint-119.c} | 6 +- ...vx_constraint-91.c => binop_vx_constraint-97.c} | 56 ++-- ...vx_constraint-64.c => binop_vx_constraint-98.c} | 32 +-- ...vx_constraint-47.c => binop_vx_constraint-99.c} | 0 ...nop_vv_constraint-1.c => unop_v_constraint-1.c} | 48 ++-- gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-1.c | 160 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-2.c | 160 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tumu-3.c | 160 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-1.c | 160 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-2.c | 160 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vnot_v_tumu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vv_tumu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_m_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_m_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_m_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_m_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_m_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_m_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_mu_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_mu_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_mu_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_mu_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_mu_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_mu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_tu_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_tu_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_tu_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_tu_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_tu_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsadd_vx_tu_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vsadd_vx_tum_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vsadd_vx_tum_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vsadd_vx_tum_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vsadd_vx_tum_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vsadd_vx_tum_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vsadd_vx_tum_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vsadd_vx_tumu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vsadd_vx_tumu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vsadd_vx_tumu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vsadd_vx_tumu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vsadd_vx_tumu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vsadd_vx_tumu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vv_tumu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vx_m_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vx_m_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vx_m_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vx_m_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vx_m_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vx_m_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_mu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_mu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_mu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_mu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_mu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_mu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vx_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vx_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vx_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vx_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vx_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vsaddu_vx_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tu_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tum_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tum_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tum_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tum_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tum_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tum_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tumu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tumu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tumu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tumu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tumu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vsaddu_vx_tumu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vv_tumu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_m_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_m_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_m_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_m_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_m_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_m_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_mu_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_mu_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_mu_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_mu_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_mu_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_mu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_tu_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_tu_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_tu_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_tu_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_tu_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssub_vx_tu_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vssub_vx_tum_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vssub_vx_tum_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vssub_vx_tum_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vssub_vx_tum_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vssub_vx_tum_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vssub_vx_tum_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vssub_vx_tumu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vssub_vx_tumu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vssub_vx_tumu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vssub_vx_tumu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vssub_vx_tumu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vssub_vx_tumu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_m-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_m-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_m-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_mu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_mu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_mu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_tu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_tu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_tu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_tum-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_tum-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_tum-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_tumu-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_tumu-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vv_tumu-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vx_m_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vx_m_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vx_m_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vx_m_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vx_m_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vx_m_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_mu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_mu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_mu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_mu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_mu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_mu_rv64-3.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vx_rv32-1.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vx_rv32-2.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vx_rv32-3.c | 157 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vx_rv64-1.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vx_rv64-2.c | 160 +++++++++++ .../gcc.target/riscv/rvv/base/vssubu_vx_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tu_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tum_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tum_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tum_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tum_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tum_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tum_rv64-3.c | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tumu_rv32-1.c | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tumu_rv32-2.c | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tumu_rv32-3.c | 157 +++++++++++ .../riscv/rvv/base/vssubu_vx_tumu_rv64-1.c | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tumu_rv64-2.c | 160 +++++++++++ .../riscv/rvv/base/vssubu_vx_tumu_rv64-3.c | 160 +++++++++++ 498 files changed, 80788 insertions(+), 239 deletions(-) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/exception-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-2.C create mode 100644 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create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tum_rv64-1.C create mode 100644 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gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv64-3.C copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-94.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-49.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-90.c => binop_vx [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-103.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-104.c copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-81.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-81.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-83.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-84.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-91.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-64.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-93.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-94.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-49.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-90.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-80.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-81.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-81.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-83.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-84.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-91.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-64.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vx_constraint-47.c => binop_vx [...] copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => unop_v_co [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_mu-1.c create mode 100644 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gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv_tu-1.c create mode 100644 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gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_rv32-1.c create mode 100644 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