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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-defconfig in repository toolchain/ci/llvm-project.
from 2db79ef32c6 [Driver] Update handling of c++ and runtime directories adds f29120658b2 [Driver][RISCV] Simplify. NFC adds 603ca511f91 [PowerPC] Add missing R_PPC_* relocation types adds 1c1e2ca0221 [ARM] Add some base fullfp16 tests. NFC adds caf8a11b656 [ARM] Promote fp16 frem adds aeade651f35 [ARM] Select fp16 fsqrt adds 2881325b17a [ARM] Select fp16 fabs adds 58a8541dcc3 [X86][AVX] combineBitcastvxi1 - peek through bitops to dete [...] adds c9f4b7d201c [ARM] Promote various fp16 math intrinsics adds 21542cd6f4c [ARM] Select a number of fp16 rounding functions adds 0dbafe191e5 [ARM] Select fp16 fma adds 352f5987952 [InstCombine] Remove OverflowCheckFlavor; NFC adds 39f2bebf415 [InstCombine] Refactor OptimizeOverflowCheck; NFCI adds 7228b50802c gn build: Merge r361664 adds d0f13e618fa [ValueTracking] Base computeOverflowForUnsignedMul() on Con [...] adds b7cc093db28 [Support] make countLeadingZeros() and countTrailingZeros() [...] adds 50c73a044f2 [SimplifyCFG] NFC, update Switch tests to HEAD so I can see [...] adds 444eaaf1cce [SimpligyCFG] NFC, remove GCD that was only used for powers of two adds 30111c786f7 [SimplifyCFG] Run ReduceSwitchRange unconditionally, generalize adds fa91ab85d9f [SimplifyCFG] ReduceSwitchRange: Improve on the case where [...] adds 9317963920a [InstCombine] prevent crashing with invalid extractelement index adds 927fe7328df [SimplifyCFG] NFC, fix failing tests from last patches. adds aabe7781a50 [LLParser] Fix uninitialized variable warnings. NFCI. adds e434368a67c Revert rL361731 : [LLParser] Fix uninitialized variable war [...] adds 7b883b7ed05 [SimplifyCFG] NFC, one more fixed test from previous push. adds a044410f37e [X86][SSE] Add shuffle combining support for ISD::ANY_EXTEN [...] adds bd324fa2273 DeleteNullPointerCheck now deletes until the end brace of t [...] adds 343578759e2 [SimplifyCFG] back out all SwitchInst commits adds a549dd25607 [MCA] Refactor the logic that computes the critical memory [...] adds 2916b9e28ca [SelectionDAG] MaskedValueIsZero - add demanded elements im [...] adds 06e02856ab5 [SelectionDAG] GetDemandedBits - cleanup to more closely ma [...] adds c2493ce4a40 [MCA][Scheduler] Improved critical memory dependency computation. adds ba447bae744 [AMDGPU] Divergence driven ISel. Assign register class [...] adds e698958ad80 [BPF] generate R_BPF_NONE relocation for BTF DataSec variables adds 11b2f4fe50d [LoopInterchange] Fix handling of LCSSA nodes defined in he [...] adds cfe08bc7d68 llvm-undname: Make demangling of MD5 names more robust adds ba883e980a9 [X86] Add test cases for D62444. NFC adds 0ff41b8a5af Revert r361356: "[MIR] Add simple PRE pass to MachineCSE"
No new revisions were added by this update.
Summary of changes: .../readability/DeleteNullPointerCheck.cpp | 9 +- .../clang-tidy/readability-delete-null-pointer.cpp | 9 + clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 44 +- .../llvm/BinaryFormat/ELFRelocs/PowerPC.def | 32 + llvm/include/llvm/CodeGen/FunctionLoweringInfo.h | 11 +- llvm/include/llvm/CodeGen/SelectionDAG.h | 11 +- llvm/include/llvm/CodeGen/TargetLowering.h | 11 +- llvm/include/llvm/CodeGen/TargetRegisterInfo.h | 5 + llvm/include/llvm/MCA/Instruction.h | 52 +- llvm/lib/Analysis/ValueTracking.cpp | 102 +- llvm/lib/CodeGen/MachineCSE.cpp | 122 +-- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 6 +- .../CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | 14 +- llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 33 +- llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h | 2 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 54 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 4 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 2 +- llvm/lib/Demangle/MicrosoftDemangle.cpp | 28 +- llvm/lib/MCA/HardwareUnits/Scheduler.cpp | 94 +- llvm/lib/MCA/Instruction.cpp | 24 +- llvm/lib/MCA/Stages/DispatchStage.cpp | 3 - llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 166 ++-- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 91 +- llvm/lib/Target/AMDGPU/SIISelLowering.h | 5 +- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 13 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 5 + llvm/lib/Target/ARM/ARMISelLowering.cpp | 22 +- llvm/lib/Target/ARM/ARMISelLowering.h | 3 +- llvm/lib/Target/ARM/ARMInstrVFP.td | 19 +- .../Target/BPF/MCTargetDesc/BPFELFObjectWriter.cpp | 32 +- .../Target/X86/MCTargetDesc/X86InstComments.cpp | 18 +- llvm/lib/Target/X86/Utils/X86ShuffleDecode.cpp | 5 +- llvm/lib/Target/X86/Utils/X86ShuffleDecode.h | 2 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 31 +- .../Transforms/InstCombine/InstCombineCalls.cpp | 11 +- .../Transforms/InstCombine/InstCombineCompares.cpp | 151 ++- .../Transforms/InstCombine/InstCombineInternal.h | 43 +- .../InstCombine/InstCombineVectorOps.cpp | 5 +- llvm/lib/Transforms/Scalar/LoopInterchange.cpp | 86 +- llvm/test/Analysis/CostModel/X86/arith-fp.ll | 171 ++++ llvm/test/CodeGen/AMDGPU/atomicrmw-nand.ll | 12 +- llvm/test/CodeGen/AMDGPU/branch-relaxation.ll | 3 +- llvm/test/CodeGen/AMDGPU/branch-uniformity.ll | 4 +- .../CodeGen/AMDGPU/control-flow-fastregalloc.ll | 7 +- .../AMDGPU/divergent-branch-uniform-condition.ll | 55 +- .../CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll | 6 +- llvm/test/CodeGen/AMDGPU/fabs.ll | 12 +- llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll | 58 +- llvm/test/CodeGen/AMDGPU/fmin_legacy.ll | 8 +- llvm/test/CodeGen/AMDGPU/fneg-fabs.ll | 16 +- llvm/test/CodeGen/AMDGPU/fsub.ll | 12 +- llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll | 10 +- .../CodeGen/AMDGPU/i1-copy-phi-uniform-branch.ll | 1 - llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll | 6 +- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll | 2 +- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.ll | 8 +- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll | 2 + .../CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll | 2 +- .../CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll | 2 +- llvm/test/CodeGen/AMDGPU/loop_break.ll | 8 +- llvm/test/CodeGen/AMDGPU/madak.ll | 12 +- .../test/CodeGen/AMDGPU/mubuf-legalize-operands.ll | 5 +- llvm/test/CodeGen/AMDGPU/multilevel-break.ll | 5 +- llvm/test/CodeGen/AMDGPU/select-opt.ll | 4 +- llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll | 3 +- llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir | 2 +- llvm/test/CodeGen/AMDGPU/smrd.ll | 1 - .../CodeGen/AMDGPU/subreg-coalescer-undef-use.ll | 53 +- .../AMDGPU/uniform-loop-inside-nonuniform.ll | 5 +- .../test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll | 9 +- llvm/test/CodeGen/AMDGPU/valu-i1.ll | 6 +- .../vgpr-spill-emergency-stack-slot-compute.ll | 1 + llvm/test/CodeGen/ARM/fp16-fullfp16.ll | 606 ++++++++++++ llvm/test/CodeGen/ARM/fp16-instructions.ll | 13 - llvm/test/CodeGen/BPF/reloc-btf-2.ll | 60 ++ llvm/test/CodeGen/Mips/internalfunc.ll | 3 +- llvm/test/CodeGen/X86/avx2-masked-gather.ll | 48 +- llvm/test/CodeGen/X86/bitcast-and-setcc-256.ll | 28 +- llvm/test/CodeGen/X86/masked_compressstore.ll | 1013 ++++++++++++-------- llvm/test/CodeGen/X86/masked_gather.ll | 94 +- llvm/test/CodeGen/X86/masked_store.ll | 722 ++++++++------ llvm/test/CodeGen/X86/masked_store_trunc.ll | 531 +++++----- llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll | 527 ++++++---- llvm/test/CodeGen/X86/masked_store_trunc_usat.ll | 535 ++++++----- llvm/test/CodeGen/X86/shrink_vmul.ll | 52 +- llvm/test/Demangle/ms-md5.test | 16 +- llvm/test/Transforms/InstCombine/extractelement.ll | 19 + .../Transforms/LoopInterchange/perserve-lcssa.ll | 181 ++++ .../tools/llvm-mca/X86/BtVer2/bottleneck-hints-3.s | 2 +- .../clang/lib/StaticAnalyzer/Checkers/BUILD.gn | 1 + 91 files changed, 4102 insertions(+), 2240 deletions(-) create mode 100644 llvm/test/CodeGen/ARM/fp16-fullfp16.ll create mode 100644 llvm/test/CodeGen/BPF/reloc-btf-2.ll create mode 100644 llvm/test/Transforms/LoopInterchange/perserve-lcssa.ll