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from be3fec6 [LV] Process pointer IVs with PHINodes in collectLoopUniforms new 8bc95d0 AMDGPU: Improve splitting 64-bit bit ops by constants new f4559b5 getScalarType().getSizeInBits() -> getScalarSizeInBits() ; NFCI
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Summary of changes: lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 64 ++++---- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 4 +- lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 8 +- lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 6 +- lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 36 ++--- lib/CodeGen/SelectionDAG/TargetLowering.cpp | 22 +-- lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 2 +- lib/Target/AArch64/AArch64ISelLowering.cpp | 2 +- lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 46 ++---- lib/Target/AMDGPU/AMDGPUISelLowering.h | 5 +- lib/Target/AMDGPU/SIFoldOperands.cpp | 126 ++++++++++++++++ lib/Target/AMDGPU/SIISelLowering.cpp | 173 +++++++++++++++------- lib/Target/AMDGPU/SIISelLowering.h | 6 + lib/Target/AMDGPU/SIInstructions.td | 4 +- lib/Target/ARM/ARMISelLowering.cpp | 2 +- lib/Target/PowerPC/PPCISelLowering.cpp | 2 +- lib/Target/SystemZ/SystemZOperators.td | 4 +- lib/Target/X86/X86ISelLowering.cpp | 2 +- test/CodeGen/AMDGPU/and.ll | 14 ++ test/CodeGen/AMDGPU/bitreverse.ll | 3 +- test/CodeGen/AMDGPU/bswap.ll | 4 +- test/CodeGen/AMDGPU/constant-fold-mi-operands.ll | 144 ++++++++++++++++++ test/CodeGen/AMDGPU/ctpop64.ll | 3 +- test/CodeGen/AMDGPU/or.ll | 102 ++++++++++++- test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll | 1 - test/CodeGen/AMDGPU/sint_to_fp.i64.ll | 1 + test/CodeGen/AMDGPU/xor.ll | 78 ++++++++++ 27 files changed, 691 insertions(+), 173 deletions(-) create mode 100644 test/CodeGen/AMDGPU/constant-fold-mi-operands.ll