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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-allmodconfig in repository toolchain/ci/qemu.
from d495e432c0 Merge tag 'pull-aspeed-20220630' of https://github.com/legoa [...] adds af2ae2e8ac bsd-user: Implement mount, umount and nmount adds c7b62b4a87 bsd-user: Implement symlink, symlinkat, readlink and readlinkat adds 0db0db8f23 bsd-user: implement chmod, fchmod, lchmod and fchmodat adds 79cfae0c1b bsd-user: Implement freebsd11_mknod, freebsd11_mknodat and mknodat adds 58af3e295c bsd-user: Implement chown, fchown, lchown and fchownat adds c6f0a7d91a bsd-user: Implement chflags, lchflags and fchflags adds 17a4d13cea bsd-user: Implement chroot and flock adds 5fbd8011ff bsd-user: Implement mkfifo and mkfifoat adds d3f29ddacd bsd-user: Implement pathconf, lpathconf and fpathconf adds 952d5d30d6 bsd-user: Implement undelete adds 3f1b0235f6 bsd-user: Remove stray 'inline' from do_bsd_close adds ba45b82518 Merge tag 'bsd-user-syscall-2022q2b-pull-request' of ssh://g [...] adds 4e245a9e26 target/riscv: Remove condition guarding register zero for au [...] adds b97028b8c5 target/riscv: Set env->bins in gen_exception_illegal adds 5dacdbaeaf target/riscv: Remove generate_exception_mtval adds a9814e3e08 target/riscv: Minimize the calls to decode_save_opc adds 2e98339918 target/riscv/pmp: guard against PMP ranges with a negative size adds 562009e47c target/riscv: Fix PMU CSR predicate function adds a5a92fd6ef target/riscv: Implement PMU CSR predicate function for S-mode adds d3be1299fb target/riscv: pmu: Rename the counters extension to pmu adds 18d6d89efc target/riscv: pmu: Make number of counters configurable adds b1675eeb3e target/riscv: Implement mcountinhibit CSR adds 621f35bb2f target/riscv: Add support for hpmcounters/hpmevents adds 3780e33732 target/riscv: Support mcycle/minstret write operation adds b509caceaa target/riscv: Fixup MSECCFG minimum priv check adds be2265c776 target/riscv: Ibex: Support priv version 1.11 adds 188000952c target/riscv: Don't force update priv spec version to latest adds ec2c62dacc hw/riscv: boot: Reduce FDT address alignment constraints adds 598ca83706 target/riscv: Set minumum priv spec version for mcountinhibit adds df01af337f target/riscv: Remove CSRs that set/clear an IMSIC interrupt [...] adds 435774992e target/riscv: Update default priority table for local interrupts adds e8e86b484e Merge tag 'pull-riscv-to-apply-20220703-1' of github.com:ali [...] adds 8e72ceee5c Rename docs/specs/fw_cfg.txt to .rst adds 701caa3d6a Convert fw_cfg.rst to reStructuredText syntax adds 839a482695 ui/console: allow display device to be labeled with given id adds 8c0d80245f ui/cocoa: Fix clipboard text release adds ada270cd18 hw/usb/canokey: Fix CCID ZLP adds 1042563027 hw/usb/canokey: fix compatibility of qemu-xhci adds 8607b5149e docs/system/devices/usb/canokey: remove limitations on qemu-xhci adds 927b968d1b hw: canokey: Remove HS support as not compliant to the spec adds dfe2382f06 Merge tag 'kraxel-20220704-pull-request' of https://gitlab.c [...] adds 070f735333 linux-user: Add LoongArch generic header files adds 9d5cd6587a linux-user: Add LoongArch signal support adds 3418fe25fa linux-user: Add LoongArch elf support adds 1f63019632 linux-user: Add LoongArch syscall support adds da8c70ea82 linux-user: Add LoongArch cpu_loop support adds 0caebb9160 scripts: add loongarch64 binfmt config adds fffca8f227 target/loongarch: remove badaddr from CPULoongArch adds 7d552f0e0a target/loongarch: Fix missing update CSR_BADV adds 7fe7eea6ff target/loongarch: Fix helper_asrtle_d/asrtgt_d raise wrong e [...] adds 9bc92b5013 target/loongarch: remove unused include hw/loader.h adds 0093b9a5ee target/loongarch: Adjust functions and structure to support [...] adds d32688ecdb default-configs: Add loongarch linux-user support adds 227e73c986 target/loongarch: Update README adds 490c03ab11 hw/intc/loongarch_pch_msi: Fix msi vector convertion adds 4f2c65877c hw/rtc/ls7a_rtc: Fix uninitialied bugs and toymatch writing [...] adds df11f3ea69 hw/rtc/ls7a_rtc: Fix timer call back function adds 53a5eb2e7a hw/rtc/ls7a_rtc: Remove unimplemented device in realized function adds e5c0367e2b hw/rtc/ls7a_rtc: Add reset function adds 6935f132e5 hw/rtc/ls7a_rtc: Fix rtc enable and disable function adds 582788c3fb hw/rtc/ls7a_rtc: Use tm struct pointer as arguments in toy_t [...] adds 59e52dcff7 hw/rtc/ls7a_rtc: Fix 'calculate' spelling errors adds 4623367697 target/loongarch: Fix the meaning of ECFG reg's VS field adds eb1e9ff8bb target/loongarch: Add lock when writing timer clear reg adds 1437479e5e Merge tag 'pull-la-20220704' of https://gitlab.com/rth7680/q [...] adds c1ca312a6f hw/rtc/ls7a_rtc: Drop unused inline functions adds 3517fb7267 target/loongarch: Clean up tlb when cpu reset adds f8d1ae8262 scripts/qemu-binfmt-conf: Add LoongArch to qemu_get_family() adds 0df0a66555 tcg/tci: Remove CONFIG_DEBUG_TCG_INTERPRETER adds ddf9326184 hw/intc/loongarch_ipi: Fix ipi device access of 64bits adds bf7ce37f8f hw/intc/loongarch_ipi: Fix mail send and any send function adds 19361471b5 Merge tag 'pull-la-20220705' of https://gitlab.com/rth7680/q [...] adds 9323af2e81 tests: fix test-cutils leaks adds e0a2602070 tests/fp: Do not build softfloat3 tests if TCG is disabled adds 94b731874a gitlab: normalize indentation in edk2/opensbi rules adds 37a2b95231 gitlab: tweak comments in edk2/opensbi jobs adds 6e131bf69b gitlab: honour QEMU_CI variable in edk2/opensbi jobs adds 3a751770ee gitlab-ci: Extend timeout for ubuntu-20.04-s390x-all to 75m adds 276dfd03f0 tests: wait max 120 seconds for migration test status changes adds 8d4e897a99 tests: wait for migration completion before looking for STOP event adds 6843ad8c03 tests: increase migration test converge downtime to 30 seconds adds 886dfe9db3 tests: use consistent bandwidth/downtime limits in migration tests adds 2116650254 disas: Remove libvixl disassembler adds 6d17020a80 po: add ukrainian translation adds 1ec8c2c01e meson.build: Require a recent version of libpng adds 7a890b7566 include/qemu/host-utils: Remove unused code in the *_overflo [...] adds d82423a697 Merge tag 'pull-request-2022-07-05' of https://gitlab.com/th [...]
No new revisions were added by this update.
Summary of changes: .gitlab-ci.d/custom-runners/ubuntu-20.04-s390x.yml | 1 + .gitlab-ci.d/edk2.yml | 133 +- .gitlab-ci.d/opensbi.yml | 134 +- MAINTAINERS | 4 - bsd-user/bsd-file.h | 392 +- bsd-user/freebsd/os-syscall.c | 118 + configs/targets/loongarch64-linux-user.mak | 3 + disas.c | 3 - disas/arm-a64.cc | 101 - disas/libvixl/LICENCE | 30 - disas/libvixl/README | 11 - disas/libvixl/meson.build | 7 - disas/libvixl/vixl/a64/assembler-a64.h | 4624 -------------------- disas/libvixl/vixl/a64/constants-a64.h | 2116 --------- disas/libvixl/vixl/a64/cpu-a64.h | 83 - disas/libvixl/vixl/a64/decoder-a64.cc | 877 ---- disas/libvixl/vixl/a64/decoder-a64.h | 275 -- disas/libvixl/vixl/a64/disasm-a64.cc | 3495 --------------- disas/libvixl/vixl/a64/disasm-a64.h | 177 - disas/libvixl/vixl/a64/instructions-a64.cc | 622 --- disas/libvixl/vixl/a64/instructions-a64.h | 757 ---- disas/libvixl/vixl/code-buffer.h | 113 - disas/libvixl/vixl/compiler-intrinsics.cc | 144 - disas/libvixl/vixl/compiler-intrinsics.h | 155 - disas/libvixl/vixl/globals.h | 155 - disas/libvixl/vixl/invalset.h | 775 ---- disas/libvixl/vixl/platform.h | 39 - disas/libvixl/vixl/utils.cc | 142 - disas/libvixl/vixl/utils.h | 286 -- disas/meson.build | 5 - docs/specs/{fw_cfg.txt => fw_cfg.rst} | 211 +- docs/specs/index.rst | 1 + docs/system/devices/canokey.rst | 10 - hw/intc/loongarch_ipi.c | 92 +- hw/intc/loongarch_pch_msi.c | 22 +- hw/loongarch/loongson3.c | 6 +- hw/riscv/boot.c | 4 +- hw/rtc/ls7a_rtc.c | 154 +- hw/usb/canokey.c | 31 +- include/exec/poison.h | 2 - include/hw/intc/loongarch_ipi.h | 7 +- include/hw/intc/loongarch_pch_msi.h | 2 + include/qemu/host-utils.h | 65 - include/ui/console.h | 1 + linux-user/elfload.c | 91 + linux-user/loongarch64/cpu_loop.c | 96 + linux-user/loongarch64/signal.c | 335 ++ linux-user/loongarch64/sockbits.h | 11 + linux-user/loongarch64/syscall_nr.h | 312 ++ linux-user/loongarch64/target_cpu.h | 34 + linux-user/loongarch64/target_elf.h | 12 + linux-user/loongarch64/target_errno_defs.h | 12 + linux-user/loongarch64/target_fcntl.h | 11 + linux-user/{arm => loongarch64}/target_prctl.h | 0 linux-user/loongarch64/target_resource.h | 11 + linux-user/loongarch64/target_signal.h | 13 + linux-user/loongarch64/target_structs.h | 11 + linux-user/loongarch64/target_syscall.h | 48 + linux-user/loongarch64/termbits.h | 11 + linux-user/syscall_defs.h | 6 +- meson.build | 6 +- po/LINGUAS | 1 + po/uk.po | 75 + scripts/clean-header-guards.pl | 4 +- scripts/clean-includes | 2 +- scripts/coverity-scan/COMPONENTS.md | 3 - scripts/gensyscalls.sh | 2 + scripts/qemu-binfmt-conf.sh | 9 +- target/arm/cpu.c | 7 - target/loongarch/README | 39 +- target/loongarch/cpu.c | 39 +- target/loongarch/cpu.h | 8 +- target/loongarch/csr_helper.c | 2 + target/loongarch/gdbstub.c | 2 +- target/loongarch/helper.h | 2 + target/loongarch/insn_trans/trans_privileged.c.inc | 36 + target/loongarch/internals.h | 2 + target/loongarch/op_helper.c | 10 +- target/riscv/cpu.c | 17 +- target/riscv/cpu.h | 24 +- target/riscv/cpu_bits.h | 30 +- target/riscv/cpu_helper.c | 134 +- target/riscv/csr.c | 857 ++-- target/riscv/insn_trans/trans_privileged.c.inc | 4 + target/riscv/insn_trans/trans_rvh.c.inc | 2 + target/riscv/insn_trans/trans_rvi.c.inc | 10 +- target/riscv/machine.c | 25 + target/riscv/meson.build | 3 +- target/riscv/pmp.c | 3 + target/riscv/pmu.c | 32 + target/riscv/pmu.h | 28 + target/riscv/translate.c | 31 +- tcg/tci/tcg-target.c.inc | 7 - tcg/tci/tcg-target.h | 5 - tests/fp/meson.build | 3 + tests/qtest/migration-helpers.c | 14 + tests/qtest/migration-test.c | 59 +- tests/tcg/riscv64/Makefile.softmmu-target | 21 + tests/tcg/riscv64/issue1060.S | 53 + tests/tcg/riscv64/semihost.ld | 21 + tests/unit/test-cutils.c | 42 +- ui/cocoa.m | 4 +- ui/console.c | 41 +- 103 files changed, 3158 insertions(+), 15960 deletions(-) create mode 100644 configs/targets/loongarch64-linux-user.mak delete mode 100644 disas/arm-a64.cc delete mode 100644 disas/libvixl/LICENCE delete mode 100644 disas/libvixl/README delete mode 100644 disas/libvixl/meson.build delete mode 100644 disas/libvixl/vixl/a64/assembler-a64.h delete mode 100644 disas/libvixl/vixl/a64/constants-a64.h delete mode 100644 disas/libvixl/vixl/a64/cpu-a64.h delete mode 100644 disas/libvixl/vixl/a64/decoder-a64.cc delete mode 100644 disas/libvixl/vixl/a64/decoder-a64.h delete mode 100644 disas/libvixl/vixl/a64/disasm-a64.cc delete mode 100644 disas/libvixl/vixl/a64/disasm-a64.h delete mode 100644 disas/libvixl/vixl/a64/instructions-a64.cc delete mode 100644 disas/libvixl/vixl/a64/instructions-a64.h delete mode 100644 disas/libvixl/vixl/code-buffer.h delete mode 100644 disas/libvixl/vixl/compiler-intrinsics.cc delete mode 100644 disas/libvixl/vixl/compiler-intrinsics.h delete mode 100644 disas/libvixl/vixl/globals.h delete mode 100644 disas/libvixl/vixl/invalset.h delete mode 100644 disas/libvixl/vixl/platform.h delete mode 100644 disas/libvixl/vixl/utils.cc delete mode 100644 disas/libvixl/vixl/utils.h rename docs/specs/{fw_cfg.txt => fw_cfg.rst} (58%) create mode 100644 linux-user/loongarch64/cpu_loop.c create mode 100644 linux-user/loongarch64/signal.c create mode 100644 linux-user/loongarch64/sockbits.h create mode 100644 linux-user/loongarch64/syscall_nr.h create mode 100644 linux-user/loongarch64/target_cpu.h create mode 100644 linux-user/loongarch64/target_elf.h create mode 100644 linux-user/loongarch64/target_errno_defs.h create mode 100644 linux-user/loongarch64/target_fcntl.h copy linux-user/{arm => loongarch64}/target_prctl.h (100%) create mode 100644 linux-user/loongarch64/target_resource.h create mode 100644 linux-user/loongarch64/target_signal.h create mode 100644 linux-user/loongarch64/target_structs.h create mode 100644 linux-user/loongarch64/target_syscall.h create mode 100644 linux-user/loongarch64/termbits.h create mode 100644 po/uk.po create mode 100644 target/riscv/pmu.c create mode 100644 target/riscv/pmu.h create mode 100644 tests/tcg/riscv64/Makefile.softmmu-target create mode 100644 tests/tcg/riscv64/issue1060.S create mode 100644 tests/tcg/riscv64/semihost.ld