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from d9d6774527b amdgcn: implement vector div and mod libfuncs new 2ba7347aba5 RISC-V: Bugfix for RVV float reduction in ZVE32/64 new 26bb67fc4d4 RISC-V: Bugfix for RVV widenning reduction in ZVE32/64
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Summary of changes: gcc/config/riscv/riscv-vector-builtins-bases.cc | 19 +- gcc/config/riscv/vector-iterators.md | 231 ++------ gcc/config/riscv/vector.md | 606 +++++++++++++-------- .../gcc.target/riscv/rvv/base/pr110277-1.c | 9 + .../gcc.target/riscv/rvv/base/pr110277-1.h | 33 ++ .../gcc.target/riscv/rvv/base/pr110277-2.c | 11 + .../gcc.target/riscv/rvv/base/pr110277-2.h | 33 ++ .../gcc.target/riscv/rvv/base/pr110299-1.c | 7 + .../gcc.target/riscv/rvv/base/pr110299-1.h | 9 + .../gcc.target/riscv/rvv/base/pr110299-2.c | 8 + .../gcc.target/riscv/rvv/base/pr110299-2.h | 17 + .../gcc.target/riscv/rvv/base/pr110299-3.c | 7 + .../gcc.target/riscv/rvv/base/pr110299-3.h | 17 + .../gcc.target/riscv/rvv/base/pr110299-4.c | 8 + .../gcc.target/riscv/rvv/base/pr110299-4.h | 17 + 15 files changed, 618 insertions(+), 414 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110277-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110277-1.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110277-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110277-2.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-3.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.h