This is an automated email from the git hooks/post-receive script.
unknown user pushed a change to branch master in repository llvm.
from 799e36774a9 [Debug] Add dbg.value intrinsics for PHIs created during LCSSA. new 13357c96d2d [MachineOperand][Target] MachineOperand::isRenamable semant [...]
The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: include/llvm/CodeGen/MachineInstr.h | 3 +-- include/llvm/CodeGen/MachineOperand.h | 39 ++++++++++++++++++++++------- include/llvm/Target/Target.td | 6 +++++ lib/CodeGen/MachineInstr.cpp | 6 +---- lib/CodeGen/MachineOperand.cpp | 30 +++++++++++----------- lib/CodeGen/MachineVerifier.cpp | 10 +++----- lib/CodeGen/RegAllocFast.cpp | 4 +-- lib/CodeGen/VirtRegMap.cpp | 2 +- lib/Target/AArch64/AArch64.td | 1 + lib/Target/AMDGPU/AMDGPU.td | 1 + lib/Target/AMDGPU/SIInsertSkips.cpp | 5 ---- lib/Target/AMDGPU/SIInstrFormats.td | 5 ++-- lib/Target/AMDGPU/SIOptimizeExecMasking.cpp | 4 +-- lib/Target/AMDGPU/VOPInstructions.td | 2 -- lib/Target/ARM/ARM.td | 1 + lib/Target/ARM/ARMBaseInstrInfo.cpp | 4 --- lib/Target/ARM/ARMExpandPseudoInsts.cpp | 3 --- lib/Target/ARM/ARMISelLowering.cpp | 2 -- lib/Target/Hexagon/Hexagon.td | 1 + lib/Target/Hexagon/RDFCopy.cpp | 3 --- lib/Target/Mips/Mips.td | 1 + lib/Target/PowerPC/PPC.td | 1 + lib/Target/RISCV/RISCV.td | 1 + lib/Target/Sparc/Sparc.td | 1 + lib/Target/SystemZ/SystemZ.td | 1 + lib/Target/X86/X86.td | 1 + lib/Target/X86/X86FloatingPoint.cpp | 3 --- test/CodeGen/AMDGPU/postra-norename.mir | 13 ++++++++++ utils/TableGen/CodeGenTarget.cpp | 3 +++ utils/TableGen/CodeGenTarget.h | 5 ++++ utils/TableGen/InstrInfoEmitter.cpp | 9 ++++--- 31 files changed, 100 insertions(+), 71 deletions(-) create mode 100644 test/CodeGen/AMDGPU/postra-norename.mir