This is an automated email from the git hooks/post-receive script.
tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/llvm-master-arm-spec2k6-Os in repository toolchain/ci/llvm-project.
from 9a0900dc4c6 [NFC][AIX][XCOFF] Fix compile warning on strncpy adds 9cf511aa08a [RISCV] Add intrinsics for vector AMO operations adds a11f8b1ad66 [libc++] [P0935] [C++20] Eradicating unnecessarily explicit [...] adds d4bb3ef5327 [libc][NFC] Remove dead code adds e517dff50a4 [libc][NFC] remove dependency on non standard ssize_t adds b86e7ae66cb [clang][driver][NFC][obvious] Remove obsolete unistd.h include adds 418df4a6ab3 [WebAssembly] call_indirect issues table number relocs adds 831a143e50c [WebAssembly] Change prefix on data segment flags to WASM_D [...] adds 39a2a233f88 [clang][cli] Parse Lang and CodeGen options separately adds 7e1d2224b42 [X86][AMX] Fix the typo. adds c3ce2627949 [NFC] Make remaining cost functions in LoopVectorize.cpp us [...] adds 170199f5626 [llvm][nvptx] add atomicity to counter in ISelLowering adds 95b63c7b139 [ORC] Move LookupRequest from OrcShared to Orc. adds fb5b12e42ef [lit] Harmonize lit and llvm versionning adds a003f26539c [llvm] Prevent infinite loop in InstCombine of select statements adds c81ea9429f8 [RISCV] Add scalable-vector integer extension patterns adds 9a7672ac498 [lldb] Fix crash in "help memory read" adds 244ad228f34 [ARM][MachineOutliner] Add stack fixup feature adds 079e6646617 [lldb] Re-enable TestPlatformProcessConnect on macos adds e448ad787e1 [LLDB] Add support to resize SVE registers at run-time adds 4d3081331ad [LLDB] Test SVE dynamic resize with multiple threads adds 83daa49758a [LoopRotate] Add PrepareForLTO stage, avoid rotating with i [...] adds 49dce85584e [AMDGPU] Simplify AMDGPUInstPrinter::printExpSrcN. NFC. adds 58bdfcfac04 Revert 5238e7b302 "[InstCombine] Replace one-use select ope [...] adds 5626adcd6bb [X86][SSE] combineVectorSignBitsTruncation - fold trunc(srl [...] adds c9439ca3634 [AArch64][SVE] Coalesce calls to the SVE ptrue intrinsic wh [...]
No new revisions were added by this update.
Summary of changes: clang/include/clang/Driver/Options.td | 17 +- clang/include/clang/Frontend/CompilerInvocation.h | 3 +- clang/lib/Driver/ToolChains/Clang.cpp | 4 - clang/lib/Frontend/CompilerInvocation.cpp | 81 +- clang/lib/Headers/amxintrin.h | 2 +- clang/test/CodeGen/X86/amx_api.c | 8 +- clang/test/Frontend/diagnostics-order.c | 2 +- libc/benchmarks/JSON.cpp | 5 - libc/benchmarks/LibcMemoryBenchmarkMain.cpp | 2 - libc/src/string/memmove.cpp | 24 +- libcxx/docs/Cxx2aStatusPaperStatus.csv | 2 +- libcxx/include/algorithm | 12 +- libcxx/include/locale | 42 +- libcxx/include/queue | 19 +- libcxx/include/random | 276 +- libcxx/include/regex | 10 +- libcxx/include/sstream | 89 +- libcxx/include/strstream | 10 +- .../priqueue.cons/ctor_comp.pass.cpp | 14 +- .../priqueue.cons/ctor_comp_container.pass.cpp | 19 +- .../priqueue.cons/ctor_comp_rcontainer.pass.cpp | 15 +- .../priqueue.cons/ctor_default.pass.cpp | 18 +- .../queue/queue.cons/ctor_container.pass.cpp | 15 +- .../queue/queue.cons/ctor_default.pass.cpp | 18 +- .../queue/queue.cons/ctor_rcontainer.pass.cpp | 19 +- .../stack/stack.cons/ctor_container.pass.cpp | 17 +- .../stack/stack.cons/ctor_default.pass.cpp | 18 +- .../stack/stack.cons/ctor_rcontainer.pass.cpp | 17 +- .../depr.strstreambuf.cons/default.pass.cpp | 17 +- .../istringstream.cons/default.pass.cpp | 20 +- .../ostringstream.cons/default.pass.cpp | 20 +- .../stringbuf/stringbuf.cons/default.pass.cpp | 17 +- .../stringstream.cons/default.pass.cpp | 20 +- .../conversions/conversions.buffer/ctor.pass.cpp | 21 +- .../conversions.string/ctor_codecvt.pass.cpp | 19 +- .../std/numerics/rand/rand.device/ctor.pass.cpp | 13 +- .../rand.dist.bern.bernoulli/ctor_double.pass.cpp | 19 +- .../rand.dist.bern.bin/ctor_int_double.pass.cpp | 24 +- .../rand.dist.bern.geo/ctor_double.pass.cpp | 23 +- .../rand.dist.bern.negbin/ctor_int_double.pass.cpp | 24 +- .../ctor_double_double.pass.cpp | 24 +- .../rand.dist.norm.chisq/ctor_double.pass.cpp | 23 +- .../rand.dist.norm.f/ctor_double_double.pass.cpp | 24 +- .../ctor_double_double.pass.cpp | 24 +- .../ctor_double_double.pass.cpp | 24 +- .../rand.dist.norm.t/ctor_double.pass.cpp | 23 +- .../rand.dist.pois.exp/ctor_double.pass.cpp | 23 +- .../ctor_double_double.pass.cpp | 24 +- .../ctor_double_double.pass.cpp | 24 +- .../rand.dist.pois.poisson/ctor_double.pass.cpp | 23 +- .../ctor_double_double.pass.cpp | 24 +- .../rand.dist.uni.int/ctor_int_int.pass.cpp | 25 +- .../rand.dist.uni.real/ctor_int_int.pass.cpp | 44 - .../rand.dist.uni.real/ctor_real_real.pass.cpp | 64 + .../rand.eng.lcong/ctor_result_type.pass.cpp | 77 +- .../rand.eng.mers/ctor_result_type.pass.cpp | 39 +- .../rand.eng.sub/ctor_result_type.pass.cpp | 41 +- .../re.results/re.results.const/default.pass.cpp | 23 +- .../make_implicit.h} | 27 +- lld/test/wasm/call-indirect.ll | 6 +- lld/test/wasm/compress-relocs.ll | 2 +- lld/test/wasm/shared.ll | 8 +- lld/wasm/OutputSections.cpp | 6 +- lld/wasm/Writer.cpp | 4 +- lldb/include/lldb/Utility/OptionDefinition.h | 5 +- .../test/tools/lldb-server/lldbgdbserverutils.py | 3 - .../Linux/NativeRegisterContextLinux_arm64.cpp | 23 +- .../Process/Utility/DynamicRegisterInfo.cpp | 11 + .../Plugins/Process/Utility/DynamicRegisterInfo.h | 6 +- .../gdb-remote/GDBRemoteRegisterContext.cpp | 81 +- .../Process/gdb-remote/GDBRemoteRegisterContext.h | 3 + .../Process/gdb-remote/ProcessGDBRemote.cpp | 13 + lldb/test/API/commands/help/TestHelp.py | 5 + .../rw_access_dynamic_resize/Makefile | 5 + .../TestSVEThreadedDynamic.py | 138 + .../rw_access_dynamic_resize/main.c | 96 + .../TestPlatformProcessConnect.py | 1 - llvm/include/llvm/Analysis/CodeMetrics.h | 3 +- llvm/include/llvm/BinaryFormat/Wasm.h | 11 +- .../Orc/OrcRPCTargetProcessControl.h | 2 +- .../Orc/Shared/TargetProcessControlTypes.h | 9 - .../ExecutionEngine/Orc/TargetProcessControl.h | 12 +- llvm/include/llvm/IR/IntrinsicsRISCV.td | 28 + llvm/include/llvm/Transforms/Scalar.h | 2 +- llvm/include/llvm/Transforms/Scalar/LoopRotation.h | 4 +- .../llvm/Transforms/Utils/LoopRotationUtils.h | 3 +- llvm/lib/Analysis/CodeMetrics.cpp | 12 +- .../Orc/TPCDynamicLibrarySearchGenerator.cpp | 2 +- .../ExecutionEngine/Orc/TargetProcessControl.cpp | 3 +- llvm/lib/MC/WasmObjectWriter.cpp | 16 +- llvm/lib/Object/WasmObjectFile.cpp | 8 +- llvm/lib/ObjectYAML/WasmEmitter.cpp | 4 +- llvm/lib/ObjectYAML/WasmYAML.cpp | 4 +- llvm/lib/Passes/PassBuilder.cpp | 3 +- llvm/lib/Target/AArch64/SVEIntrinsicOpts.cpp | 222 +- .../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 21 +- .../Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h | 6 +- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 142 + llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 10 + llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 26 +- llvm/lib/Target/NVPTX/NVPTXISelLowering.h | 3 +- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 219 +- llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td | 26 + .../WebAssembly/AsmParser/WebAssemblyAsmParser.cpp | 42 +- .../MCTargetDesc/WebAssemblyInstPrinter.cpp | 2 +- .../MCTargetDesc/WebAssemblyMCTargetDesc.h | 10 + .../lib/Target/WebAssembly/WebAssemblyFastISel.cpp | 15 +- .../Target/WebAssembly/WebAssemblyISelLowering.cpp | 15 +- .../lib/Target/WebAssembly/WebAssemblyInstrCall.td | 18 +- .../Target/WebAssembly/WebAssemblyMCInstLower.cpp | 4 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 16 +- llvm/lib/Transforms/IPO/PassManagerBuilder.cpp | 4 +- .../Transforms/InstCombine/InstCombineSelect.cpp | 17 +- llvm/lib/Transforms/Scalar/LoopRotation.cpp | 29 +- llvm/lib/Transforms/Utils/LoopRotationUtils.cpp | 17 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 135 +- .../AArch64/sve-coalesce-ptrue-intrinsics.ll | 189 ++ llvm/test/CodeGen/ARM/machine-outliner-default.mir | 117 - .../CodeGen/ARM/machine-outliner-no-lr-save.mir | 56 - .../ARM/machine-outliner-stack-fixup-arm.mir | 186 ++ .../ARM/machine-outliner-stack-fixup-thumb.mir | 231 ++ llvm/test/CodeGen/RISCV/rvv/vamoadd-rv32.ll | 734 +++++ llvm/test/CodeGen/RISCV/rvv/vamoadd-rv64.ll | 1714 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vamoand-rv32.ll | 734 +++++ llvm/test/CodeGen/RISCV/rvv/vamoand-rv64.ll | 1714 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vamomax-rv32.ll | 734 +++++ llvm/test/CodeGen/RISCV/rvv/vamomax-rv64.ll | 1714 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv32.ll | 734 +++++ llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv64.ll | 1714 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vamomin-rv32.ll | 734 +++++ llvm/test/CodeGen/RISCV/rvv/vamomin-rv64.ll | 1714 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vamominu-rv32.ll | 734 +++++ llvm/test/CodeGen/RISCV/rvv/vamominu-rv64.ll | 1714 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vamoor-rv32.ll | 734 +++++ llvm/test/CodeGen/RISCV/rvv/vamoor-rv64.ll | 1714 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vamoswap-rv32.ll | 2054 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vamoswap-rv64.ll | 3426 ++++++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vamoxor-rv32.ll | 734 +++++ llvm/test/CodeGen/RISCV/rvv/vamoxor-rv64.ll | 1714 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv32.ll | 619 ++++ llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv64.ll | 619 ++++ .../test/CodeGen/WebAssembly/function-pointer64.ll | 10 +- llvm/test/CodeGen/WebAssembly/multivalue.ll | 2 +- llvm/test/CodeGen/X86/vector-trunc.ll | 7 +- llvm/test/MC/WebAssembly/basic-assembly.s | 2 +- .../{type-index.s => call-indirect-relocs.s} | 69 +- llvm/test/MC/WebAssembly/reloc-code.ll | 16 +- llvm/test/MC/WebAssembly/tail-call-encodings.s | 2 +- llvm/test/MC/WebAssembly/type-index.s | 7 +- llvm/test/MC/WebAssembly/weak-alias.s | 50 +- .../Transforms/InstCombine/select-binop-cmp.ll | 44 +- .../InstCombine/select-safe-transforms.ll | 4 +- .../Transforms/LoopRotate/call-prepare-for-lto.ll | 7 + .../Inputs/arm_generated_funcs.ll | 2 - .../arm_generated_funcs.ll.generated.expected | 35 +- .../arm_generated_funcs.ll.nogenerated.expected | 24 +- llvm/utils/lit/lit/__init__.py | 2 +- 157 files changed, 29612 insertions(+), 908 deletions(-) delete mode 100644 libcxx/test/std/numerics/rand/rand.dis/rand.dist.uni/rand.dist. [...] create mode 100644 libcxx/test/std/numerics/rand/rand.dis/rand.dist.uni/rand.dist. [...] copy libcxx/test/{std/containers/container.adaptors/priority.queue/priqueue.cons/c [...] create mode 100644 lldb/test/API/commands/register/register/aarch64_sve_registers/ [...] create mode 100644 lldb/test/API/commands/register/register/aarch64_sve_registers/ [...] create mode 100644 lldb/test/API/commands/register/register/aarch64_sve_registers/ [...] create mode 100644 llvm/test/CodeGen/AArch64/sve-coalesce-ptrue-intrinsics.ll create mode 100644 llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-arm.mir create mode 100644 llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir create mode 100644 llvm/test/CodeGen/RISCV/rvv/vamoadd-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vamoadd-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vamoand-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vamoand-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vamomax-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vamomax-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vamomin-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vamomin-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vamominu-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vamominu-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vamoor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vamoor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vamoswap-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vamoswap-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vamoxor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vamoxor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv64.ll copy llvm/test/MC/WebAssembly/{type-index.s => call-indirect-relocs.s} (50%)