[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allmodconfig updated (107198fe7de8 -> f59cc9542bfb)

10 Oct 2021


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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allmodconfig
in repository toolchain/ci/llvm-project.
from  107198fe7de8 Fix memory leaks in mlir/unittests/MLIRTableGenTests
      adds  57d9adefa04d Fix memory leaks in MLIR unit-tests (NFC)
      adds  9312cb6f2092 Fix Undefined Behavior in MLIR Diagnostic: don't call memc [...]
      adds  fe48ecb047fa Fix memory leak in mlir-cpu-runner/sgemm_naive_codegen.mlir (NFC)
      adds  4b28638bcc7a Fix multiple memory leaks in mlir-cpu-runner tests (NFC)
      adds  bac4529b4397 Fix/disable more MLIR tests exposing leaks in ASAN builds (NFC)
      adds  2da3facd864c Fix memory leak in MLIR SPIRV ModuleCombiner
      adds  8320017b79eb [libc++] [ranges] Uncomment operator<=> in transform and i [...]
      adds  e8806d748643 Re-apply the fix on DwarfEHPrepare and add a test
      adds  060a96a7b5d5 [LLVM][IR] Fixed input arguments for Verifier getter
      adds  51b9f0b82ab1 Fix memory leaks in MLIR integration tests for vector dial [...]
      adds  5de44d25213c Disable leak check for the MLIR Sparse CPU integration tes [...]
      adds  903facd96b1d Disable leak check for the MLIR Linalg CPU integration tes [...]
      adds  0b83a35caf22 [MLIR][NFC] Drop unnecessary use of OpBuilder in build tri [...]
      adds  d6a4294d1362 Use standard separator for TSan options in `stress.cpp` te [...]
      adds  b2d078fb0cac [IR]PATCH 1/2: Add AsmWriterContext into AsmWriter
      adds  475de8da011c [IR]PATCH 2/2: Add MDNode::printTree and dumpTree
      adds  cb2e0eb68e67 Fix last leaky MLIR integration test (NFC)
      adds  86f50288989a Exclude MLIR python binding tests from Sanitizer tests for now
      adds  bce0c6429ee3 Fix ASAN execution for the MLIR Python tests
      adds  93769e81ed2e [mlir] [test] Include mlir_tools_dir in PATH to fix mlir-reduce
      adds  c274384cff1b [NFC][RISCV] Update test cases through update_cc_test_checks.py.
      adds  cf284f6c5ef3 [LSV] Change the default value of InstertElement to poison
      adds  f62d18ff140f [Clang] Extend -Wbool-operation to warn about bitwise and  [...]
      adds  a4933f57f3f0 Revert "[Clang] Extend -Wbool-operation to warn about bitw [...]
      adds  b1fcca388441 Fixed warnings in LLVM produced by -Wbitwise-instead-of-logical
      adds  f59cc9542bfb Reland "[Clang] Extend -Wbool-operation to warn about bitw [...]
No new revisions were added by this update.
Summary of changes:
 clang/include/clang/Basic/DiagnosticGroups.td      |   3 +-
 clang/include/clang/Basic/DiagnosticSemaKinds.td   |   4 +
 clang/lib/AST/Type.cpp                             |   4 +-
 clang/lib/CodeGen/CGExpr.cpp                       |   6 +-
 clang/lib/Sema/SemaChecking.cpp                    |  16 +-
 clang/lib/Sema/SemaExpr.cpp                        |   2 +-
 .../RISCV/rvv-intrinsics-overloaded/vaadd.c        |  88 ----
 .../CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c |  88 ----
 .../CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c | 176 ++++++++
 .../RISCV/rvv-intrinsics-overloaded/vamoadd.c      | 140 -------
 .../RISCV/rvv-intrinsics-overloaded/vamoand.c      | 140 -------
 .../RISCV/rvv-intrinsics-overloaded/vamomax.c      | 140 -------
 .../RISCV/rvv-intrinsics-overloaded/vamomin.c      | 140 -------
 .../RISCV/rvv-intrinsics-overloaded/vamoor.c       | 140 -------
 .../RISCV/rvv-intrinsics-overloaded/vamoswap.c     | 210 ----------
 .../RISCV/rvv-intrinsics-overloaded/vamoxor.c      | 140 -------
 .../CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c |  88 ----
 .../RISCV/rvv-intrinsics-overloaded/vasub.c        |  88 ----
 .../CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c |  88 ----
 .../RISCV/rvv-intrinsics-overloaded/vfabs.c        |   9 -
 .../RISCV/rvv-intrinsics-overloaded/vfadd.c        |  29 ++
 .../RISCV/rvv-intrinsics-overloaded/vfclass.c      |  18 -
 .../RISCV/rvv-intrinsics-overloaded/vfcvt.c        |  54 ---
 .../RISCV/rvv-intrinsics-overloaded/vfdiv.c        |  18 -
 .../RISCV/rvv-intrinsics-overloaded/vfirst.c       |  14 -
 .../RISCV/rvv-intrinsics-overloaded/vfmacc.c       |  36 --
 .../RISCV/rvv-intrinsics-overloaded/vfmadd.c       |  36 --
 .../RISCV/rvv-intrinsics-overloaded/vfmax.c        |  18 -
 .../RISCV/rvv-intrinsics-overloaded/vfmerge.c      |   9 -
 .../RISCV/rvv-intrinsics-overloaded/vfmin.c        |  18 -
 .../RISCV/rvv-intrinsics-overloaded/vfmsac.c       |  36 --
 .../RISCV/rvv-intrinsics-overloaded/vfmsub.c       |  36 --
 .../RISCV/rvv-intrinsics-overloaded/vfmul.c        |  18 -
 .../CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c |  18 -
 .../RISCV/rvv-intrinsics-overloaded/vfncvt.c       |  52 ---
 .../RISCV/rvv-intrinsics-overloaded/vfneg.c        |   9 -
 .../RISCV/rvv-intrinsics-overloaded/vfnmacc.c      |  36 --
 .../RISCV/rvv-intrinsics-overloaded/vfnmadd.c      |  36 --
 .../RISCV/rvv-intrinsics-overloaded/vfnmsac.c      |  36 --
 .../RISCV/rvv-intrinsics-overloaded/vfnmsub.c      |  36 --
 .../RISCV/rvv-intrinsics-overloaded/vfrdiv.c       |   9 -
 .../RISCV/rvv-intrinsics-overloaded/vfrec7.c       |   9 -
 .../RISCV/rvv-intrinsics-overloaded/vfredmax.c     |  18 -
 .../RISCV/rvv-intrinsics-overloaded/vfredmin.c     |  18 -
 .../RISCV/rvv-intrinsics-overloaded/vfredsum.c     |  36 --
 .../RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c     |   9 -
 .../RISCV/rvv-intrinsics-overloaded/vfrsub.c       |   9 -
 .../RISCV/rvv-intrinsics-overloaded/vfsgnj.c       |  54 ---
 .../RISCV/rvv-intrinsics-overloaded/vfslide1down.c |   9 -
 .../RISCV/rvv-intrinsics-overloaded/vfslide1up.c   |   9 -
 .../RISCV/rvv-intrinsics-overloaded/vfsqrt.c       |   9 -
 .../RISCV/rvv-intrinsics-overloaded/vfsub.c        |  18 -
 .../RISCV/rvv-intrinsics-overloaded/vfwadd.c       |  16 -
 .../RISCV/rvv-intrinsics-overloaded/vfwcvt.c       |  38 --
 .../RISCV/rvv-intrinsics-overloaded/vfwmacc.c      |  16 -
 .../RISCV/rvv-intrinsics-overloaded/vfwmsac.c      |  16 -
 .../RISCV/rvv-intrinsics-overloaded/vfwmul.c       |   8 -
 .../RISCV/rvv-intrinsics-overloaded/vfwnmacc.c     |  16 -
 .../RISCV/rvv-intrinsics-overloaded/vfwnmsac.c     |  16 -
 .../RISCV/rvv-intrinsics-overloaded/vfwredsum.c    |  20 -
 .../RISCV/rvv-intrinsics-overloaded/vfwsub.c       |  16 -
 .../CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c  |  22 -
 .../RISCV/rvv-intrinsics-overloaded/viota.c        |  22 -
 .../RISCV/rvv-intrinsics-overloaded/vloxei.c       | 191 ---------
 .../RISCV/rvv-intrinsics-overloaded/vluxei.c       | 191 ---------
 .../RISCV/rvv-intrinsics-overloaded/vmacc.c        | 176 --------
 .../RISCV/rvv-intrinsics-overloaded/vmadc.c        | 176 --------
 .../RISCV/rvv-intrinsics-overloaded/vmadd.c        | 176 --------
 .../RISCV/rvv-intrinsics-overloaded/vmand.c        |  14 -
 .../CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c |  88 ----
 .../RISCV/rvv-intrinsics-overloaded/vmerge.c       |  97 -----
 .../RISCV/rvv-intrinsics-overloaded/vmfeq.c        |  36 --
 .../RISCV/rvv-intrinsics-overloaded/vmfge.c        |  36 --
 .../RISCV/rvv-intrinsics-overloaded/vmfgt.c        |  36 --
 .../RISCV/rvv-intrinsics-overloaded/vmfle.c        |  36 --
 .../RISCV/rvv-intrinsics-overloaded/vmflt.c        |  36 --
 .../RISCV/rvv-intrinsics-overloaded/vmfne.c        |  36 --
 .../CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c |  88 ----
 .../CodeGen/RISCV/rvv-intrinsics-overloaded/vmmv.c |   7 -
 .../RISCV/rvv-intrinsics-overloaded/vmnand.c       |   7 -
 .../RISCV/rvv-intrinsics-overloaded/vmnor.c        |   7 -
 .../RISCV/rvv-intrinsics-overloaded/vmnot.c        |   7 -
 .../CodeGen/RISCV/rvv-intrinsics-overloaded/vmor.c |  14 -
 .../RISCV/rvv-intrinsics-overloaded/vmsbc.c        | 176 --------
 .../RISCV/rvv-intrinsics-overloaded/vmsbf.c        |  14 -
 .../RISCV/rvv-intrinsics-overloaded/vmseq.c        | 176 --------
 .../RISCV/rvv-intrinsics-overloaded/vmsge.c        | 176 --------
 .../RISCV/rvv-intrinsics-overloaded/vmsgt.c        | 176 --------
 .../RISCV/rvv-intrinsics-overloaded/vmsif.c        |  14 -
 .../RISCV/rvv-intrinsics-overloaded/vmsle.c        | 176 --------
 .../RISCV/rvv-intrinsics-overloaded/vmslt.c        | 176 --------
 .../RISCV/rvv-intrinsics-overloaded/vmsne.c        | 176 --------
 .../RISCV/rvv-intrinsics-overloaded/vmsof.c        |  14 -
 .../CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c | 220 ----------
 .../CodeGen/RISCV/rvv-intrinsics-overloaded/vmv.c  | 141 -------
 .../RISCV/rvv-intrinsics-overloaded/vmxnor.c       |   7 -
 .../RISCV/rvv-intrinsics-overloaded/vmxor.c        |   7 -
 .../RISCV/rvv-intrinsics-overloaded/vnclip.c       |  60 ---
 .../RISCV/rvv-intrinsics-overloaded/vncvt.c        |  30 --
 .../CodeGen/RISCV/rvv-intrinsics-overloaded/vneg.c |  22 -
 .../RISCV/rvv-intrinsics-overloaded/vnmsac.c       | 176 --------
 .../RISCV/rvv-intrinsics-overloaded/vnmsub.c       | 176 --------
 .../CodeGen/RISCV/rvv-intrinsics-overloaded/vnot.c |  44 --
 .../RISCV/rvv-intrinsics-overloaded/vnsra.c        |  30 --
 .../RISCV/rvv-intrinsics-overloaded/vnsrl.c        |  30 --
 .../CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c  |  88 ----
 .../RISCV/rvv-intrinsics-overloaded/vpopc.c        |  14 -
 .../RISCV/rvv-intrinsics-overloaded/vredand.c      |  88 ----
 .../RISCV/rvv-intrinsics-overloaded/vredmax.c      |  88 ----
 .../RISCV/rvv-intrinsics-overloaded/vredmin.c      |  88 ----
 .../RISCV/rvv-intrinsics-overloaded/vredor.c       |  88 ----
 .../RISCV/rvv-intrinsics-overloaded/vredsum.c      |  88 ----
 .../RISCV/rvv-intrinsics-overloaded/vredxor.c      |  88 ----
 .../CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c |  88 ----
 .../RISCV/rvv-intrinsics-overloaded/vrgather.c     | 157 -------
 .../RISCV/rvv-intrinsics-overloaded/vrsub.c        |  44 --
 .../RISCV/rvv-intrinsics-overloaded/vsadd.c        |  88 ----
 .../CodeGen/RISCV/rvv-intrinsics-overloaded/vsbc.c |  88 ----
 .../RISCV/rvv-intrinsics-overloaded/vsext.c        |  28 --
 .../RISCV/rvv-intrinsics-overloaded/vslide1down.c  |  44 --
 .../RISCV/rvv-intrinsics-overloaded/vslide1up.c    |  44 --
 .../RISCV/rvv-intrinsics-overloaded/vslidedown.c   | 106 -----
 .../RISCV/rvv-intrinsics-overloaded/vslideup.c     | 106 -----
 .../CodeGen/RISCV/rvv-intrinsics-overloaded/vsll.c |  88 ----
 .../RISCV/rvv-intrinsics-overloaded/vsmul.c        |  44 --
 .../CodeGen/RISCV/rvv-intrinsics-overloaded/vsra.c |  44 --
 .../CodeGen/RISCV/rvv-intrinsics-overloaded/vsrl.c |  44 --
 .../RISCV/rvv-intrinsics-overloaded/vssra.c        |  44 --
 .../RISCV/rvv-intrinsics-overloaded/vssrl.c        |  44 --
 .../RISCV/rvv-intrinsics-overloaded/vssub.c        |  88 ----
 .../CodeGen/RISCV/rvv-intrinsics-overloaded/vsub.c |  88 ----
 .../RISCV/rvv-intrinsics-overloaded/vwadd.c        | 120 ------
 .../RISCV/rvv-intrinsics-overloaded/vwcvt.c        |  30 --
 .../RISCV/rvv-intrinsics-overloaded/vwmacc.c       | 210 ----------
 .../RISCV/rvv-intrinsics-overloaded/vwmul.c        |  90 ----
 .../RISCV/rvv-intrinsics-overloaded/vwredsum.c     |  72 ----
 .../RISCV/rvv-intrinsics-overloaded/vwsub.c        | 120 ------
 .../CodeGen/RISCV/rvv-intrinsics-overloaded/vxor.c |  88 ----
 .../RISCV/rvv-intrinsics-overloaded/vzext.c        |  28 --
 clang/test/Misc/warning-wall.c                     |   1 +
 clang/test/Sema/warn-bitwise-and-bool.c            |  63 +++
 clang/test/Sema/warn-bitwise-or-bool.c             |  63 +++
 compiler-rt/test/tsan/stress.cpp                   |   2 +-
 libcxx/include/__ranges/iota_view.h                |  21 +-
 libcxx/include/__ranges/transform_view.h           |  23 +-
 .../range.transform/iterator/compare.pass.cpp      |  74 ++--
 .../ranges/range.adaptors/range.transform/types.h  |   8 -
 .../range.iota.view/iterator/compare.pass.cpp      | 112 ++---
 llvm/include/llvm/IR/Metadata.h                    |  25 ++
 llvm/lib/CodeGen/DwarfEHPrepare.cpp                |   5 +
 llvm/lib/IR/AsmWriter.cpp                          | 455 ++++++++++++---------
 llvm/lib/IR/Verifier.cpp                           |  10 +-
 .../Transforms/Vectorize/LoadStoreVectorizer.cpp   |   2 +-
 llvm/test/CodeGen/X86/dwarf-eh-prepare.ll          |   2 +-
 .../LoadStoreVectorizer/AMDGPU/merge-stores.ll     |   4 +-
 .../LoadStoreVectorizer/AMDGPU/pointer-elements.ll |   8 +-
 .../LoadStoreVectorizer/int_sideeffect.ll          |   4 +-
 llvm/unittests/IR/MetadataTest.cpp                 |  61 +++
 llvm/unittests/Support/TargetParserTest.cpp        |   6 +-
 llvm/utils/TableGen/CodeGenDAGPatterns.cpp         |   6 +-
 mlir/include/mlir/Analysis/LoopAnalysis.h          |   6 +-
 mlir/lib/Analysis/LoopAnalysis.cpp                 |  20 +-
 .../Linking/ModuleCombiner/ModuleCombiner.cpp      |  10 +-
 mlir/lib/IR/Diagnostics.cpp                        |   4 +-
 mlir/lib/Transforms/Utils/LoopUtils.cpp            |   2 +-
 mlir/test/CAPI/pass.c                              |   2 +
 mlir/test/Examples/standalone/lit.local.cfg        |   5 +
 mlir/test/IR/invalid.mlir                          |   3 +
 mlir/test/IR/opaque_locations.mlir                 |  10 +-
 .../Integration/Dialect/Linalg/CPU/lit.local.cfg   |   3 +
 .../Dialect/SparseTensor/CPU/lit.local.cfg         |   3 +
 .../Standard/CPU/test-ceil-floor-pos-neg.mlir      |   1 +
 .../Dialect/Vector/CPU/test-compress.mlir          |   1 +
 .../Dialect/Vector/CPU/test-expand.mlir            |   1 +
 .../Dialect/Vector/CPU/test-gather.mlir            |   1 +
 .../Dialect/Vector/CPU/test-maskedload.mlir        |   1 +
 .../Dialect/Vector/CPU/test-maskedstore.mlir       |   1 +
 .../Dialect/Vector/CPU/test-scatter.mlir           |   1 +
 .../Dialect/Vector/CPU/test-transfer-read-3d.mlir  |   1 +
 .../Dialect/Vector/CPU/test-transfer-read.mlir     |   3 +
 .../Dialect/Vector/CPU/test-transfer-write.mlir    |   1 +
 mlir/test/Pass/crash-recovery.mlir                 |   3 +
 mlir/test/lib/IR/TestOpaqueLoc.cpp                 |   2 +-
 mlir/test/lit.cfg.py                               |  12 +-
 mlir/test/mlir-cpu-runner/copy.mlir                |   6 +-
 .../mlir-cpu-runner/memref_reinterpret_cast.mlir   |   1 +
 mlir/test/mlir-cpu-runner/memref_reshape.mlir      |   2 +
 mlir/test/mlir-cpu-runner/sgemm_naive_codegen.mlir |   3 +
 mlir/test/mlir-cpu-runner/unranked_memref.mlir     |   3 +-
 mlir/test/python/lit.local.cfg                     |   1 +
 mlir/unittests/Rewrite/PatternBenefit.cpp          |   5 +-
 191 files changed, 949 insertions(+), 9147 deletions(-)
 create mode 100644 clang/test/Sema/warn-bitwise-and-bool.c
 create mode 100644 clang/test/Sema/warn-bitwise-or-bool.c
 create mode 100644 mlir/test/Integration/Dialect/Linalg/CPU/lit.local.cfg
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[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allmodconfig updated (107198fe7de8 -> f59cc9542bfb)