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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/qemu.
from a92cecba27 Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-2021 [...] adds 9925c8bb81 hw/riscv: virt: Don't use a macro for the PLIC configuration adds bf357e1d72 hw/riscv: boot: Add a PLIC config string function adds 4e8fb53c0b hw/riscv: sifive_u: Use the PLIC config helper function adds 8486eb8cdc hw/riscv: microchip_pfsoc: Use the PLIC config helper function adds 7d10ff8a4d hw/riscv: virt: Use the PLIC config helper function adds 9b144ed444 hw/riscv: opentitan: Fixup the PLIC context addresses adds 53dcea58b8 target/riscv: Add J-extension into RISC-V adds 138b5c5f8f target/riscv: Add CSR defines for RISC-V PM extension adds 4bbe8033fc target/riscv: Support CSRs required for RISC-V PM extension [...] adds b1c279e135 target/riscv: Add J extension state description adds bd5594ca28 target/riscv: Print new PM CSRs in QEMU logs adds c655df7fe0 target/riscv: Support pointer masking for RISC-V for i/c/f/d [...] adds 0774a7a1ff target/riscv: Implement address masking functions required f [...] adds 0ee9a4e57e target/riscv: Allow experimental J-ext to be turned on adds 487a99551a target/riscv: fix VS interrupts forwarding to HS adds 50d1608764 target/riscv: remove force HS exception adds 0e9030376e softfloat: add APIs to handle alternative sNaN propagation f [...] adds 15161e425e target/riscv: change the api for RVF/RVD fmin/fmax adds 6450ce5634 Merge remote-tracking branch 'remotes/alistair23/tags/pull-r [...]
No new revisions were added by this update.
Summary of changes: fpu/softfloat-parts.c.inc | 25 ++- fpu/softfloat.c | 19 ++- hw/riscv/boot.c | 25 +++ hw/riscv/microchip_pfsoc.c | 14 +- hw/riscv/opentitan.c | 4 +- hw/riscv/sifive_u.c | 14 +- hw/riscv/virt.c | 20 +-- include/fpu/softfloat.h | 10 ++ include/hw/riscv/boot.h | 2 + include/hw/riscv/microchip_pfsoc.h | 1 - include/hw/riscv/sifive_u.h | 1 - include/hw/riscv/virt.h | 1 - target/riscv/cpu.c | 13 ++ target/riscv/cpu.h | 17 +- target/riscv/cpu_bits.h | 102 +++++++++++- target/riscv/cpu_helper.c | 72 +++----- target/riscv/csr.c | 285 ++++++++++++++++++++++++++++++++ target/riscv/fpu_helper.c | 16 +- target/riscv/insn_trans/trans_rva.c.inc | 3 + target/riscv/insn_trans/trans_rvd.c.inc | 2 + target/riscv/insn_trans/trans_rvf.c.inc | 2 + target/riscv/insn_trans/trans_rvi.c.inc | 2 + target/riscv/machine.c | 27 +++ target/riscv/translate.c | 43 +++++ 24 files changed, 605 insertions(+), 115 deletions(-)