This is an automated email from the git hooks/post-receive script.
tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allnoconfig in repository toolchain/ci/llvm-project.
from 706b48251f6 [InstCombine] canonicalize fcmp+select to minnum/maxnum intrinsics adds 135cf982e8e Revert "[GDBRemote] Remove code that flushes GDB remote packets" adds bb0b44deaab Clean up MSVC visualization of LLVM pointer types adds fb133b0aabe Various tweaks to MSVC natvis visualizers adds d1728f89878 [X86] Add MOVHPDrm/MOVLPDrm patterns that use VZEXT_LOAD. adds fc233c9108d [X86] Add some additional load folding tests to vec_int_to_ [...] adds 4ca81a9b994 [X86] Add a DAG combine to replace vector loads feeding a v [...] adds 29fff0797b2 [X86] Improve the type checking fast-isel handling of vecto [...] adds fcda45a9eb8 [X86] Add more load folding tests for vcvt(t)ps2(u)qq showi [...] adds b739b91cd3a [clangd] Make FixIt message be consistent with the clang-ti [...] adds 0384a780549 [libcxx] [test] Add void cast to result of compare_exchange [...] adds 98722691b0b [ARM] WLS/LE Code Generation adds d4097b4a93a [SimpleLoopUnswitch] Implement handling of prof branch_weig [...] adds 9d34f4569b4 [clangd] Show better message when we rename macros. adds d2b6665e339 [DebugInfo] Avoid adding too much indirection to pointer-va [...] adds 0f82f64c832 [NFC][InstCombine] Copy test for omit urem when possible fr [...] adds f55818e3a72 [InstCombine] Omit 'urem' where possible adds 4f878fe3a7d [NFC][InstCombine] Tests for x - ~(y) -> x + y + 1 fold ( [...] adds 9cca81344c8 [clangd] Make PreambleStatusCache handle filenames more carefully adds 60300c9c7d6 [clangd] Fix unused var from r364735 adds d74f2d0a860 [benchmark] Disable CMake get_git_version adds ed13fef4774 [SelectionDAG] Do minnum->minimum at legalization time inst [...] adds 0f73709cb71 Remove null checks of results of new expressions adds 172fe5dd191 [X86] CombineShuffleWithExtract - updated description comme [...] adds 92e78b7bedb [RISCV] Add break; to the last switch case adds 881aab4dc3d [clangd] No longer getting template instantiations from hea [...] adds 4f0a3772805 Fix TestGdbRemoteLibrariesSvr4Support adds d5c3e34cb7e [NFC][InstCombine] Tests for ((~x) + y) + 1 -> y - x fold [...] adds 33c8c0ea275 [AMDGPU] Call isLoopExiting for blocks in the loop. adds 08c38f77c5f Revert "Implement xfer:libraries-svr4:read packet" adds 17c3eafb2e3 [ASTImporter] Propagate error from ImportDeclContext adds 77c04c3a577 @skipIfXmlSupportMissing TestRecognizeBreakpoint new c12dfcf1f56 Don't check the validity of newly contructed data buffers new 3a10810b7ab [mips] Add missing schedinfo for ADJCALLSTACKDOWN, ADJCALLSTACKUP new c0121bf8741 [mips] Add missing schedinfo for atomic instructions new ceb9da5bc79 [mips] Add missing schedinfo for MSA and ASE instructions new fbf67d88de2 GlobalISel: Add DAG compat for G_FCANONICALIZE new 01bb075c1f9 GlobalISel: Add GINodeEquiv for min/max new 5dafcb9b118 AMDGPU/GlobalISel: Use and instead of BFE with inline immediate new 9f992c238ab AMDGPU/GlobalISel: Fix scc->vcc copy handling new facf69e8449 AMDGPU/GlobalISel: Use vcc reg bank for amdgcn.wqm.vote new c23149f612d AMDGPU/GlobalISel: RegBankSelect for WWM/WQM new 9f3645869cf [NFC][InstCombine] Improve test coverage for ((~x) + y) + [...] new 3b7668ae4bb AMDGPU/GlobalISel: Improve icmp selection coverage. new 89fc8bcdd6d AMDGPU/GlobalISel: Fail on store to 32-bit address space new b5fc94f3e74 AMDGPU/GlobalISel: Fix RegBankSelect for G_BUILD_VECTOR new 5bf850d52e0 AMDGPU/GlobalISel: Fix RegBankSelect for G_FCANONICALIZE new 1b317685e9b AMDGPU: Convert some places to Register
The 16 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: clang-tools-extra/clangd/ClangdUnit.cpp | 3 +- clang-tools-extra/clangd/Diagnostics.cpp | 2 + clang-tools-extra/clangd/FS.cpp | 19 +- clang-tools-extra/clangd/SourceCode.cpp | 27 + clang-tools-extra/clangd/SourceCode.h | 8 + clang-tools-extra/clangd/XRefs.cpp | 76 +- clang-tools-extra/clangd/refactor/Rename.cpp | 43 +- .../clangd/unittests/ClangdUnitTests.cpp | 20 + .../clangd/unittests/DiagnosticsTests.cpp | 22 +- clang-tools-extra/clangd/unittests/FSTests.cpp | 12 +- clang-tools-extra/clangd/unittests/RenameTests.cpp | 7 + .../clangd/unittests/SourceCodeTests.cpp | 17 + clang/lib/AST/ASTImporter.cpp | 33 +- clang/unittests/AST/ASTImporterTest.cpp | 87 +++ clang/utils/ClangVisualizers/clang.natvis | 54 +- .../atomics.general/replace_failure_order.pass.cpp | 8 +- .../lldb/Host/common/NativeProcessProtocol.h | 14 - .../gdb_remote_client/TestRecognizeBreakpoint.py | 1 + .../test/tools/lldb-server/gdbremote_testcase.py | 29 +- .../test/tools/lldb-server/libraries-svr4/Makefile | 17 - .../TestGdbRemoteLibrariesSvr4Support.py | 130 ---- .../test/tools/lldb-server/libraries-svr4/main.cpp | 15 - .../tools/lldb-server/libraries-svr4/svr4lib_a.cpp | 9 - .../tools/lldb-server/libraries-svr4/svr4lib_a.mk | 9 - .../lldb-server/libraries-svr4/svr4lib_b_quote.cpp | 9 - .../lldb-server/libraries-svr4/svr4lib_b_quote.mk | 9 - .../Plugins/ObjectFile/JIT/ObjectFileJIT.cpp | 14 +- .../RegisterContextPOSIXProcessMonitor_arm.cpp | 2 +- .../RegisterContextPOSIXProcessMonitor_arm64.cpp | 2 +- .../RegisterContextPOSIXProcessMonitor_mips64.cpp | 2 +- .../RegisterContextPOSIXProcessMonitor_powerpc.cpp | 2 +- .../RegisterContextPOSIXProcessMonitor_x86.cpp | 2 +- .../Plugins/Process/Linux/NativeProcessLinux.cpp | 2 +- .../Linux/NativeRegisterContextLinux_arm.cpp | 11 - .../Linux/NativeRegisterContextLinux_arm64.cpp | 11 - .../Linux/NativeRegisterContextLinux_mips64.cpp | 14 - .../Linux/NativeRegisterContextLinux_ppc64le.cpp | 11 - .../Linux/NativeRegisterContextLinux_s390x.cpp | 14 - .../Plugins/Process/NetBSD/NativeProcessNetBSD.h | 4 +- .../NetBSD/NativeRegisterContextNetBSD_x86_64.cpp | 14 - .../Plugins/Process/POSIX/NativeProcessELF.cpp | 69 -- .../Plugins/Process/POSIX/NativeProcessELF.h | 7 - .../Utility/RegisterContextDarwin_arm64.cpp | 4 +- .../Process/Utility/RegisterContextDarwin_i386.cpp | 3 +- .../Utility/RegisterContextDarwin_x86_64.cpp | 3 +- .../gdb-remote/GDBRemoteCommunicationClient.cpp | 7 + .../GDBRemoteCommunicationServerCommon.cpp | 1 - .../GDBRemoteCommunicationServerLLGS.cpp | 43 -- .../gdb-remote/GDBRemoteCommunicationServerLLGS.h | 2 - llvm/include/llvm/IR/DebugInfoMetadata.h | 4 + .../llvm/Target/GlobalISel/SelectionDAGCompat.td | 5 + llvm/lib/CodeGen/HardwareLoops.cpp | 1 + llvm/lib/CodeGen/PrologEpilogInserter.cpp | 13 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 22 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 11 + llvm/lib/IR/DebugInfoMetadata.cpp | 21 + llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h | 15 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 122 +++- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 2 + llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 8 +- .../Target/AMDGPU/AMDGPUTargetTransformInfo.cpp | 6 +- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 4 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 4 +- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 10 + llvm/lib/Target/ARM/ARMISelLowering.cpp | 42 ++ llvm/lib/Target/ARM/ARMISelLowering.h | 2 + llvm/lib/Target/ARM/ARMInstrInfo.td | 8 + llvm/lib/Target/ARM/ARMInstrThumb2.td | 10 +- llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp | 116 ++- llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp | 2 + llvm/lib/Target/Mips/MipsDSPInstrInfo.td | 1 + llvm/lib/Target/Mips/MipsInstrInfo.td | 11 +- llvm/lib/Target/Mips/MipsMSAInstrInfo.td | 7 +- llvm/lib/Target/Mips/MipsScheduleP5600.td | 22 + llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 1 + llvm/lib/Target/X86/X86FastISel.cpp | 21 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 36 +- llvm/lib/Target/X86/X86InstrAVX512.td | 22 + llvm/lib/Target/X86/X86InstrSSE.td | 12 + .../Transforms/InstCombine/InstCombineCompares.cpp | 24 +- llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp | 56 +- .../AMDGPU/GlobalISel/inst-select-anyext.mir | 36 + .../CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir | 114 ++- .../GlobalISel/inst-select-fcanonicalize.mir | 169 +++++ .../AMDGPU/GlobalISel/inst-select-icmp.s64.mir | 595 +++++++++++++++ .../AMDGPU/GlobalISel/inst-select-implicit-def.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir | 39 + .../CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir | 83 +++ .../CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir | 83 +++ .../CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir | 83 +++ .../CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir | 83 +++ .../CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir | 48 +- .../AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir | 31 + ...-vote.mir => regbankselect-amdgcn.wqm.vote.mir} | 10 +- .../AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir | 31 + .../GlobalISel/regbankselect-build-vector.mir | 69 ++ .../GlobalISel/regbankselect-fcanonicalize.mir | 35 + .../Thumb2/LowOverheadLoops}/cond-mov.mir | 0 .../CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll | 213 ++++++ .../Thumb2/LowOverheadLoops}/massive.mir | 0 .../LowOverheadLoops}/multiblock-massive.mir | 0 .../Thumb2/LowOverheadLoops}/revert-after-call.mir | 0 .../LowOverheadLoops}/revert-after-spill.mir | 0 .../Thumb2/LowOverheadLoops/revert-while.mir | 130 ++++ .../Thumb2/LowOverheadLoops}/size-limit.mir | 0 .../Thumb2/LowOverheadLoops}/switch.mir | 0 .../test/CodeGen/Thumb2/LowOverheadLoops/while.mir | 131 ++++ llvm/test/CodeGen/WebAssembly/f32.ll | 18 + llvm/test/CodeGen/WebAssembly/simd-arith.ll | 22 + llvm/test/CodeGen/X86/avx512dqvl-intrinsics.ll | 747 +++++++++++++++++++ .../CodeGen/X86/merge-consecutive-loads-128.ll | 3 +- llvm/test/CodeGen/X86/pr42452.ll | 37 + llvm/test/CodeGen/X86/vec_fp_to_int-widen.ll | 152 ++++ llvm/test/CodeGen/X86/vec_fp_to_int.ll | 152 ++++ llvm/test/CodeGen/X86/vec_int_to_fp-widen.ll | 794 +++++++++++++++++---- llvm/test/CodeGen/X86/vec_int_to_fp.ll | 472 ++++++++---- .../MIR/X86/prolog-epilog-indirection.mir | 130 ++++ llvm/test/Transforms/HardwareLoops/ARM/do-rem.ll | 32 +- .../Transforms/HardwareLoops/ARM/fp-emulation.ll | 23 +- .../test/Transforms/HardwareLoops/ARM/simple-do.ll | 42 +- .../test/Transforms/HardwareLoops/ARM/structure.ll | 95 ++- ...ld-inc-of-add-of-not-x-and-y-to-sub-x-from-y.ll | 224 ++++++ .../InstCombine/fold-sub-of-not-to-inc-of-add.ll | 94 +++ ...ower-of-two-or-zero-when-comparing-with-zero.ll | 166 +++++ .../SimpleLoopUnswitch/basictest-profmd.ll | 34 + .../SimpleLoopUnswitch/trivial-unswitch-profmd.ll | 228 ++++++ llvm/utils/LLVMVisualizers/llvm.natvis | 19 +- llvm/utils/benchmark/CMakeLists.txt | 7 +- llvm/utils/benchmark/README.LLVM | 2 + 129 files changed, 5927 insertions(+), 1120 deletions(-) delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s64.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir rename llvm/test/CodeGen/AMDGPU/GlobalISel/{regbankselect-amdgcn-wqm-vote.mir => r [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] create mode 100644 llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] create mode 100644 llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] create mode 100644 llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir create mode 100644 llvm/test/CodeGen/X86/pr42452.ll create mode 100644 llvm/test/DebugInfo/MIR/X86/prolog-epilog-indirection.mir create mode 100644 llvm/test/Transforms/InstCombine/fold-inc-of-add-of-not-x-and-y [...] create mode 100644 llvm/test/Transforms/InstCombine/fold-sub-of-not-to-inc-of-add.ll create mode 100644 llvm/test/Transforms/InstCombine/omit-urem-of-power-of-two-or-z [...] create mode 100644 llvm/test/Transforms/SimpleLoopUnswitch/basictest-profmd.ll create mode 100644 llvm/test/Transforms/SimpleLoopUnswitch/trivial-unswitch-profmd.ll