[Tcwg-commits] [gcc] branch master updated (a75fa2518d4 -> 81f0945cd97)

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unknown user pushed a change to branch master in repository gcc.

from a75fa2518d4 RISC-V: Add vmseq vv C++ tests new 272e119d972 RISC-V: Finish all integer C/C++ intrinsics new a432d0d9e06 RISC-V: Add vwmacc vx C api tests new 645bfe04ce1 RISC-V: Add vwmacc vv C api tests new 51307617b4a RISC-V: Add vnmsub vv C api tests new a462e612073 RISC-V: Add vnmsub vx rv64 C api tests new 496ae797c20 RISC-V: Add vnmsub vx rv32 C api tests new 3a70551148e RISC-V: Add vnmsac rv64 C api tests new 1d403b1e79f RISC-V: Add vnmsac vx C api tests new 46444e3984a RISC-V: Add vnmsac vv C api tests new 0bca2036dc7 RISC-V: Add vmadd vx rv64 c api tests new 0033ab7b923 RISC-V: Add vmadd vx c api tests new abbfd706cee RISC-V: Add vmadd vv C api tests new 987f4bb2f8d RISC-V: Add vmacc vx c api tests new dce0e53cf62 RISC-V: Add vmacc vx rv32 c api tests new ddd7c2e9489 RISC-V: Add vmacc vv c api tests new 5cf9afc5965 RISC-V: Add ternary constraint tests new c4e2a63e462 RISC-V: Add vwmacc vx C++ api tests new a5012e90b25 RISC-V: Add vwmacc vv C++ api tests new 326fe0f2f55 RISC-V: Add vnmsub vx rv64 c++ api tests new 1ff4063f258 RISC-V: Add vnmsub vx rv32 c++ api tests new 249be04bb83 RISC-V: Add vnmsub vv c++ api tests new 7ce337324a8 RISC-V: Add vnmsac vx rv64 C++ api tests new 0fd29de569b RISC-V: Add vnmsac vx C++ api tests new 47919b0decb RISC-V: Add vnmsac vv c++ api tests new 4e43f0cb269 RISC-V: Add vmadd vx C++ api test new 5db1182b7ca RISC-V: Add vmadd vv c++ api test new 1ec316c538a RISC-V: Add vmacc vx rv32 c++ api tests new 4a9a9a787b9 RISC-V: Add vmacc vx rv64 c++ api tests new 81f0945cd97 RISC-V: Add vmacc vv c++ api tests

The 29 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: gcc/config/riscv/predicates.md | 3 +- gcc/config/riscv/riscv-protos.h | 2 + gcc/config/riscv/riscv-v.cc | 4 +- gcc/config/riscv/riscv-vector-builtins-bases.cc | 142 +++++ gcc/config/riscv/riscv-vector-builtins-bases.h | 8 + .../riscv/riscv-vector-builtins-functions.def | 15 + gcc/config/riscv/riscv-vector-builtins.cc | 243 +++++++- gcc/config/riscv/riscv-vector-builtins.h | 2 + gcc/config/riscv/vector.md | 680 ++++++++++++++++++++- .../g++.target/riscv/rvv/base/vmacc_vv-1.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmacc_vv-2.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmacc_vv-3.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmacc_vv_mu-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vv_mu-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vv_mu-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vv_tu-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vv_tu-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vv_tu-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vv_tum-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vv_tum-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vv_tum-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vv_tumu-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vv_tumu-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vv_tumu-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_mu_rv32-1.C | 289 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_mu_rv32-2.C | 289 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_mu_rv32-3.C | 289 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_mu_rv64-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_mu_rv64-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_mu_rv64-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_rv32-1.C | 572 +++++++++++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_rv32-2.C | 572 +++++++++++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_rv32-3.C | 572 +++++++++++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_rv64-1.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_rv64-2.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_rv64-3.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_tu_rv32-1.C | 289 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_tu_rv32-2.C | 289 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_tu_rv32-3.C | 289 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_tu_rv64-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_tu_rv64-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_tu_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vmacc_vx_tum_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vmacc_vx_tum_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vmacc_vx_tum_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vmacc_vx_tum_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vmacc_vx_tum_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vmacc_vx_tum_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vmacc_vx_tumu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vmacc_vx_tumu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vmacc_vx_tumu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vmacc_vx_tumu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vmacc_vx_tumu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vmacc_vx_tumu_rv64-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vv-1.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmadd_vv-2.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmadd_vv-3.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmadd_vv_mu-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vv_mu-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vv_mu-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vv_tu-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vv_tu-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vv_tu-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vv_tum-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vv_tum-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vv_tum-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vv_tumu-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vv_tumu-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vv_tumu-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vx_mu_rv64-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vx_mu_rv64-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vx_mu_rv64-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vx_rv64-1.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmadd_vx_rv64-2.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmadd_vx_rv64-3.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmadd_vx_tu_rv64-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vx_tu_rv64-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vx_tu_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vmadd_vx_tum_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vmadd_vx_tum_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vmadd_vx_tum_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vmadd_vx_tumu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vmadd_vx_tumu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vmadd_vx_tumu_rv64-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsac_vv-1.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsac_vv-2.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsac_vv-3.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsac_vv_mu-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsac_vv_mu-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsac_vv_mu-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsac_vv_tu-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsac_vv_tu-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsac_vv_tu-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsac_vv_tum-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsac_vv_tum-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsac_vv_tum-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsac_vv_tumu-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsac_vv_tumu-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsac_vv_tumu-3.C | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv64-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsac_vx_rv32-1.C | 572 +++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsac_vx_rv32-2.C | 572 +++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsac_vx_rv32-3.C | 572 +++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsac_vx_rv64-1.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsac_vx_rv64-2.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsac_vx_rv64-3.C | 578 ++++++++++++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv64-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv-1.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv-2.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv-3.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv_mu-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv_mu-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv_mu-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv_tu-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv_tu-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv_tu-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv_tum-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv_tum-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv_tum-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv_tumu-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv_tumu-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv_tumu-3.C | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_mu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_mu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_mu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_mu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_mu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_mu_rv64-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsub_vx_rv32-1.C | 572 +++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsub_vx_rv32-2.C | 572 +++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsub_vx_rv32-3.C | 572 +++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsub_vx_rv64-1.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsub_vx_rv64-2.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsub_vx_rv64-3.C | 578 ++++++++++++++++++ .../riscv/rvv/base/vnmsub_vx_tu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tu_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tum_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tum_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tum_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tum_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tum_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tum_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tumu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tumu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tumu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tumu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tumu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tumu_rv64-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vwmacc_vv-1.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmacc_vv-2.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmacc_vv-3.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmacc_vv_mu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vv_mu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vv_mu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vv_tu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vv_tu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vv_tu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vv_tum-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vv_tum-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vv_tum-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vv_tumu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vv_tumu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vv_tumu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vx-1.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmacc_vx-2.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmacc_vx-3.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmacc_vx_mu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vx_mu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vx_mu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vx_tu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vx_tu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vx_tu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vx_tum-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vx_tum-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vx_tum-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vx_tumu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vx_tumu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vx_tumu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv-1.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv-2.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv-3.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv_mu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv_mu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv_mu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv_tu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv_tu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv_tu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv_tum-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv_tum-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv_tum-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx-1.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx-2.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx-3.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx_mu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx_mu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx_mu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx_tu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx_tu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx_tu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx_tum-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx_tum-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx_tum-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx_tumu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx_tumu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx_tumu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vv-1.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccu_vv-2.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccu_vv-3.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccu_vv_mu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vv_mu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vv_mu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vv_tu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vv_tu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vv_tu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vv_tum-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vv_tum-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vv_tum-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vv_tumu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vv_tumu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vv_tumu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vx-1.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccu_vx-2.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccu_vx-3.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccu_vx_mu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vx_mu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vx_mu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vx_tu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vx_tu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vx_tu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vx_tum-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vx_tum-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vx_tum-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vx_tumu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vx_tumu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vx_tumu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccus_vx-1.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccus_vx-2.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccus_vx-3.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccus_vx_mu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccus_vx_mu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccus_vx_mu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccus_vx_tu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccus_vx_tu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccus_vx_tu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccus_vx_tum-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccus_vx_tum-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccus_vx_tum-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccus_vx_tumu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccus_vx_tumu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccus_vx_tumu-3.C | 111 ++++ .../riscv/rvv/base/ternop_vv_constraint-1.c | 83 +++ .../riscv/rvv/base/ternop_vv_constraint-2.c | 83 +++ .../riscv/rvv/base/ternop_vx_constraint-1.c | 71 +++ .../riscv/rvv/base/ternop_vx_constraint-2.c | 38 ++ ...vx_constraint-91.c => ternop_vx_constraint-3.c} | 58 +- ...vx_constraint-91.c => ternop_vx_constraint-4.c} | 62 +- ...vx_constraint-57.c => ternop_vx_constraint-5.c} | 62 +- .../riscv/rvv/base/ternop_vx_constraint-6.c | 130 ++++ .../riscv/rvv/base/ternop_vx_constraint-7.c | 130 ++++ .../gcc.target/riscv/rvv/base/vmacc_vv-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_m-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_m-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_m-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_mu-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_mu-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_mu-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_tu-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_tu-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_tu-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_tum-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_tum-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_tum-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_tumu-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_tumu-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_tumu-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_m_rv32-1.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_m_rv32-2.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_m_rv32-3.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_m_rv64-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_m_rv64-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_m_rv64-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_mu_rv32-1.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_mu_rv32-2.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_mu_rv32-3.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_mu_rv64-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_mu_rv64-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_mu_rv64-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_rv32-1.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_rv32-2.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_rv32-3.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_rv64-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_rv64-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_rv64-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_tu_rv32-1.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_tu_rv32-2.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_tu_rv32-3.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_tu_rv64-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_tu_rv64-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_tu_rv64-3.c | 292 +++++++++ .../riscv/rvv/base/vmacc_vx_tum_rv32-1.c | 289 +++++++++ .../riscv/rvv/base/vmacc_vx_tum_rv32-2.c | 289 +++++++++ .../riscv/rvv/base/vmacc_vx_tum_rv32-3.c | 289 +++++++++ .../riscv/rvv/base/vmacc_vx_tum_rv64-1.c | 292 +++++++++ .../riscv/rvv/base/vmacc_vx_tum_rv64-2.c | 292 +++++++++ .../riscv/rvv/base/vmacc_vx_tum_rv64-3.c | 292 +++++++++ .../riscv/rvv/base/vmacc_vx_tumu_rv32-1.c | 289 +++++++++ .../riscv/rvv/base/vmacc_vx_tumu_rv32-2.c | 289 +++++++++ .../riscv/rvv/base/vmacc_vx_tumu_rv32-3.c | 289 +++++++++ .../riscv/rvv/base/vmacc_vx_tumu_rv64-1.c | 292 +++++++++ .../riscv/rvv/base/vmacc_vx_tumu_rv64-2.c | 292 +++++++++ .../riscv/rvv/base/vmacc_vx_tumu_rv64-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_m-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_m-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_m-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_mu-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_mu-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_mu-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_tu-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_tu-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_tu-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_tum-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_tum-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_tum-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_tumu-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_tumu-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_tumu-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_m_rv32-1.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_m_rv32-2.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_m_rv32-3.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_m_rv64-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_m_rv64-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_m_rv64-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_mu_rv32-1.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_mu_rv32-2.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_mu_rv32-3.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_mu_rv64-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_mu_rv64-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_mu_rv64-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_rv32-1.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_rv32-2.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_rv32-3.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_rv64-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_rv64-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_rv64-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_tu_rv32-1.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_tu_rv32-2.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_tu_rv32-3.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_tu_rv64-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_tu_rv64-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_tu_rv64-3.c | 292 +++++++++ .../riscv/rvv/base/vmadd_vx_tum_rv32-1.c | 289 +++++++++ .../riscv/rvv/base/vmadd_vx_tum_rv32-2.c | 289 +++++++++ .../riscv/rvv/base/vmadd_vx_tum_rv32-3.c | 289 +++++++++ .../riscv/rvv/base/vmadd_vx_tum_rv64-1.c | 292 +++++++++ .../riscv/rvv/base/vmadd_vx_tum_rv64-2.c | 292 +++++++++ .../riscv/rvv/base/vmadd_vx_tum_rv64-3.c | 292 +++++++++ .../riscv/rvv/base/vmadd_vx_tumu_rv32-1.c | 289 +++++++++ .../riscv/rvv/base/vmadd_vx_tumu_rv32-2.c | 289 +++++++++ .../riscv/rvv/base/vmadd_vx_tumu_rv32-3.c | 289 +++++++++ .../riscv/rvv/base/vmadd_vx_tumu_rv64-1.c | 292 +++++++++ .../riscv/rvv/base/vmadd_vx_tumu_rv64-2.c | 292 +++++++++ .../riscv/rvv/base/vmadd_vx_tumu_rv64-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_m-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_m-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_m-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_mu-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_mu-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_mu-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_tu-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_tu-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_tu-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_tum-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_tum-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_tum-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_tumu-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_tumu-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_tumu-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-1.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-2.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-3.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vx_m_rv64-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vx_m_rv64-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vx_m_rv64-3.c | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv32-1.c | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv32-2.c | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv32-3.c | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv64-1.c | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv64-2.c | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv64-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vx_rv32-1.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vx_rv32-2.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vx_rv32-3.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vx_rv64-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vx_rv64-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vx_rv64-3.c | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv32-1.c | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv32-2.c | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv32-3.c | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv64-1.c | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv64-2.c | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv64-3.c | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv32-1.c | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv32-2.c | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv32-3.c | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv64-1.c | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv64-2.c | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv64-3.c | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv32-1.c | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv32-2.c | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv32-3.c | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv64-1.c | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv64-2.c | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv64-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_m-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_m-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_m-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_mu-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_mu-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_mu-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_tu-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_tu-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_tu-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_tum-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_tum-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_tum-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_tumu-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_tumu-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_tumu-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vx_m_rv32-1.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vx_m_rv32-2.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vx_m_rv32-3.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vx_m_rv64-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vx_m_rv64-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vx_m_rv64-3.c | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_mu_rv32-1.c | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_mu_rv32-2.c | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_mu_rv32-3.c | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_mu_rv64-1.c | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_mu_rv64-2.c | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_mu_rv64-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vx_rv32-1.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vx_rv32-2.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vx_rv32-3.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vx_rv64-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vx_rv64-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vx_rv64-3.c | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tu_rv32-1.c | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tu_rv32-2.c | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tu_rv32-3.c | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tu_rv64-1.c | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tu_rv64-2.c | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tu_rv64-3.c | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tum_rv32-1.c | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tum_rv32-2.c | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tum_rv32-3.c | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tum_rv64-1.c | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tum_rv64-2.c | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tum_rv64-3.c | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tumu_rv32-1.c | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tumu_rv32-2.c | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tumu_rv32-3.c | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tumu_rv64-1.c | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tumu_rv64-2.c | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tumu_rv64-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vwmacc_vv-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_m-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_m-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_m-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_mu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_mu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_mu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tum-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tum-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tum-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tumu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tumu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tumu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_m-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_m-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_m-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_mu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_mu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_mu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_tu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_tu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_tu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_tum-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_tum-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_tum-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_tumu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_tumu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_tumu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_m-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_m-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_m-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_m-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_m-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_m-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_mu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_mu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_mu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tum-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tum-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tum-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tumu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tumu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tumu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_m-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_m-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_m-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_mu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_mu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_mu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tum-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tum-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tum-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_m-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_m-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_m-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_mu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_mu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_mu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_tu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_tu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_tu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_tum-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_tum-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_tum-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_tumu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_tumu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_tumu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_m-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_m-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_m-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_mu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_mu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_mu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_tu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_tu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_tu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_tum-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_tum-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_tum-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-3.c | 111 ++++ 630 files changed, 149864 insertions(+), 110 deletions(-) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tum_rv32-2.C create mode 100644 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