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from 69b60eb28a3 [RISCV] Implement MC layer support for the tail pseudoinstruction new 19e6e2d1156 [AArch64] preserve test intent by removing undef new 28e0f25edb0 [ARM] preserve test intent by removing undef new b231180388e [ARM] preserve test intent by removing undef new 03da9798c11 [x86] preserve test intent by removing undef new 6c8d8d769f5 [RISCV] Separate base from offset in lowerGlobalAddress
The 5 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: lib/Target/RISCV/RISCVISelLowering.cpp | 15 ++- test/CodeGen/AArch64/arm64-collect-loh.ll | 6 +- test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll | 40 ++++---- test/CodeGen/ARM/reg_sequence.ll | 8 +- test/CodeGen/RISCV/byval.ll | 20 ++-- test/CodeGen/RISCV/double-mem.ll | 6 +- test/CodeGen/RISCV/float-mem.ll | 6 +- test/CodeGen/RISCV/fp128.ll | 80 ++++++++-------- test/CodeGen/RISCV/hoist-global-addr-base.ll | 111 +++++++++++++++++++++++ test/CodeGen/RISCV/mem.ll | 6 +- test/CodeGen/RISCV/wide-mem.ll | 8 +- test/CodeGen/RISCV/zext-with-load-is-free.ll | 24 ++--- test/CodeGen/X86/2012-04-26-sdglue.ll | 15 ++- 13 files changed, 225 insertions(+), 120 deletions(-) create mode 100644 test/CodeGen/RISCV/hoist-global-addr-base.ll