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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_cross/gnu-master-aarch64-build_cross in repository toolchain/ci/qemu.
from 53c5433e84 Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-t [...] adds a27c100c23 target/hexagon: translation changes adds 4c82c2b433 target/hexagon: remove unnecessary checks in find_iclass_slots adds 1de468b398 target/hexagon: Change DECODE_MAPPED_REG operand name to OPNUM adds d9099caf04 target/hexagon: fix typo in comment adds 5f261764ce target/hexagon: remove unnecessary semicolons adds d799f8ad08 Hexagon (target/hexagon) TCG generation cleanup adds edf26ade43 Hexagon (target/hexagon) cleanup gen_log_predicated_reg_write_pair adds 2d27cebbf8 Hexagon (target/hexagon) remove unnecessary inline directives adds 7d9ab2021f Hexagon (target/hexagon) use env_archcpu and env_cpu adds 743debbc37 Hexagon (target/hexagon) properly generate TB end for DISAS_ [...] adds 6c677c60ae Hexagon (target/hexagon) decide if pred has been written at [...] adds 92cfa25fd2 Hexagon (target/hexagon) change variables from int to bool w [...] adds 85511161f7 Hexagon (target/hexagon) remove unused carry_from_add64 function adds 8c36752435 Hexagon (target/hexagon) change type of softfloat_roundingmodes adds c0336c87b7 Hexagon (target/hexagon) use softfloat default NaN and tininess adds 1cb532fe45 Hexagon (target/hexagon) replace float32_mul_pow2 with float [...] adds b3f37abdd3 Hexagon (target/hexagon) use softfloat for float-to-int conversions adds 9fe33c0e70 Hexagon (target/hexagon) cleanup ternary operators in semantics adds 80be682844 Hexagon (target/hexagon) cleanup reg_field_info definition adds a33872eb53 Hexagon (target/hexagon) move QEMU_GENERATE to only be on du [...] adds 85580a6557 Hexagon (target/hexagon) compile all debug code adds d934c16d8a Hexagon (target/hexagon) add F2_sfrecipa instruction adds dd8705bdf5 Hexagon (target/hexagon) add F2_sfinvsqrta adds da74cd2dce Hexagon (target/hexagon) add A5_ACS (vacsh) adds 0a65d28693 Hexagon (target/hexagon) add A6_vminub_RdP adds 57d352ac29 Hexagon (target/hexagon) add A4_addp_c/A4_subp_c adds 46ef47e2a7 Hexagon (target/hexagon) circular addressing adds af7f182127 Hexagon (target/hexagon) bit reverse (brev) addressing adds 0d0b91a804 Hexagon (target/hexagon) load and unpack bytes instructions adds 7aa9ffab79 Hexagon (target/hexagon) load into shifted register instructions adds e628c0156b Hexagon (target/hexagon) CABAC decode bin adds 15106f7dc3 Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-h [...] adds bcad139192 hw/isa/piix4: Use qdev_get_gpio_in_named() to get ISA IRQ adds 84c2fdc397 target/mips: Fix CACHEE opcode (CACHE using EVA addressing) adds 298d43c96b target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPG [...] adds bc2eb5ea1b target/mips: Remove spurious LOG_UNIMP of MTHC0 opcode adds df44e81703 target/mips: Migrate missing CPU fields adds 905bdf72a6 target/mips: Make check_cp0_enabled() return a boolean adds 58ecf15d76 target/mips: Simplify meson TCG rules adds 830a72301c target/mips: Move IEEE rounding mode array to new source file adds fed50ffd5c target/mips: Move msa_reset() to new source file adds adbf1be325 target/mips: Make CPU/FPU regnames[] arrays global adds 830b87ea25 target/mips: Optimize CPU/FPU regnames[] arrays adds 4f14ce4bf4 target/mips: Restrict mips_cpu_dump_state() to cpu.c adds 4d169b9cce target/mips: Turn printfpr() macro into a proper function adds 533fc64feb target/mips: Declare mips_env_set_pc() inlined in "internal.h" adds 0debf1400c target/mips: Merge do_translate_address into cpu_mips_transl [...] adds 6f4aec6a6d target/mips: Extract load/store helpers to ldst_helper.c adds 46369b50ee meson: Introduce meson_user_arch source set for arch-specifi [...] adds 6fe25ce587 target/mips: Introduce tcg-internal.h for TCG specific declarations adds 0a31c16c9c target/mips: Add simple user-mode mips_cpu_do_interrupt() adds 8074365fc7 target/mips: Add simple user-mode mips_cpu_tlb_fill() adds 44e3b05005 target/mips: Move cpu_signal_handler definition around adds 85d8da3fea target/mips: Move sysemu specific files under sysemu/ subfolder adds 137f4d87c6 target/mips: Move physical addressing code to sysemu/physaddr.c adds 8b28cde403 target/mips: Restrict cpu_mips_get_random() / update_pagemas [...] adds ad520a9784 target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder adds c284201702 target/mips: Restrict mmu_init() to TCG adds 920b48cc14 target/mips: Move tlb_helper.c to tcg/sysemu/ adds f3185ec2f3 target/mips: Restrict CPUMIPSTLBContext::map_address() handl [...] adds d60146a938 target/mips: Move Special opcodes to tcg/sysemu/special_helper.c adds ecdbcb0a94 target/mips: Move helper_cache() to tcg/sysemu/special_helper.c adds 6575529b65 target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c adds 8aa52bdc87 target/mips: Move exception management code to exception.c adds 5679479b9a target/mips: Move CP0 helpers to sysemu/cp0.c adds a2b0a27d33 target/mips: Move TCG source files under tcg/ sub directory adds db6b6f4dbf hw/mips: Restrict non-virtualized machines to TCG adds 1c13514449 gitlab-ci: Add KVM mips64el cross-build jobs adds e93d8bcf9d Merge remote-tracking branch 'remotes/philmd/tags/mips-20210 [...] adds ca0fd2e345 bsd-user: whitespace changes adds cefbade173 bsd-user: style tweak: keyword space ( adds fa0546370d bsd-user: style tweak: return is not a function, eliminate () adds 92ac45049b bsd-user: put back a break; that had gone missing... adds 58b3beb483 bsd-user: style tweak: Put {} around all if/else/for statements adds 3e13d8e34b Merge remote-tracking branch 'remotes/bsdimp/tags/pull-bsd-u [...]
No new revisions were added by this update.
Summary of changes: .gitlab-ci.d/crossbuilds.yml | 8 + MAINTAINERS | 3 +- bsd-user/bsdload.c | 55 +- bsd-user/qemu.h | 4 +- bsd-user/syscall.c | 1 + fpu/softfloat-specialize.c.inc | 3 + hw/isa/piix4.c | 5 +- hw/mips/meson.build | 9 +- linux-user/hexagon/cpu_loop.c | 2 +- meson.build | 6 + target/hexagon/arch.c | 181 +++- target/hexagon/arch.h | 9 +- target/hexagon/conv_emu.c | 177 ---- target/hexagon/conv_emu.h | 31 - target/hexagon/cpu.c | 14 +- target/hexagon/cpu.h | 5 - target/hexagon/cpu_bits.h | 2 +- target/hexagon/decode.c | 84 +- target/hexagon/fma_emu.c | 40 +- target/hexagon/gen_tcg.h | 424 ++++++++- target/hexagon/gen_tcg_funcs.py | 2 +- target/hexagon/genptr.c | 233 ++++- target/hexagon/helper.h | 23 +- target/hexagon/iclass.c | 4 - target/hexagon/imported/alu.idef | 44 + target/hexagon/imported/compare.idef | 12 +- target/hexagon/imported/encode_pp.def | 30 + target/hexagon/imported/float.idef | 32 + target/hexagon/imported/ldst.idef | 68 ++ target/hexagon/imported/macros.def | 47 + target/hexagon/imported/shift.idef | 47 + target/hexagon/insn.h | 21 +- target/hexagon/internal.h | 11 +- target/hexagon/macros.h | 118 ++- target/hexagon/meson.build | 1 - target/hexagon/op_helper.c | 392 ++++++--- target/hexagon/reg_fields.c | 3 +- target/hexagon/reg_fields.h | 4 +- target/hexagon/translate.c | 175 ++-- target/hexagon/translate.h | 9 +- target/mips/cpu.c | 281 ++---- target/mips/fpu.c | 25 + target/mips/helper.h | 183 +--- target/mips/internal.h | 107 +-- target/mips/meson.build | 53 +- target/mips/msa.c | 60 ++ target/mips/op_helper.c | 1210 -------------------------- target/mips/{ => sysemu}/addr.c | 0 target/mips/sysemu/cp0.c | 123 +++ target/mips/{ => sysemu}/cp0_timer.c | 0 target/mips/{ => sysemu}/machine.c | 21 +- target/mips/sysemu/meson.build | 7 + target/mips/sysemu/physaddr.c | 257 ++++++ target/mips/{ => tcg}/dsp_helper.c | 0 target/mips/tcg/exception.c | 167 ++++ target/mips/{ => tcg}/fpu_helper.c | 8 - target/mips/tcg/ldst_helper.c | 288 ++++++ target/mips/{ => tcg}/lmmi_helper.c | 0 target/mips/{ => tcg}/meson.build | 39 +- target/mips/{ => tcg}/mips32r6.decode | 0 target/mips/{ => tcg}/mips64r6.decode | 0 target/mips/{ => tcg}/msa32.decode | 0 target/mips/{ => tcg}/msa64.decode | 0 target/mips/{ => tcg}/msa_helper.c | 36 - target/mips/{ => tcg}/msa_helper.h.inc | 0 target/mips/{ => tcg}/msa_translate.c | 0 target/mips/{ => tcg}/mxu_translate.c | 0 target/mips/tcg/op_helper.c | 420 +++++++++ target/mips/{ => tcg}/rel6_translate.c | 0 target/mips/{ => tcg/sysemu}/cp0_helper.c | 0 target/mips/tcg/sysemu/meson.build | 6 + target/mips/{ => tcg/sysemu}/mips-semi.c | 0 target/mips/tcg/sysemu/special_helper.c | 173 ++++ target/mips/{ => tcg/sysemu}/tlb_helper.c | 623 +++++++------ target/mips/tcg/sysemu_helper.h.inc | 185 ++++ target/mips/tcg/tcg-internal.h | 64 ++ target/mips/{ => tcg}/translate.c | 115 +-- target/mips/{ => tcg}/translate_addr_const.c | 0 target/mips/{ => tcg}/tx79.decode | 0 target/mips/{ => tcg}/tx79_translate.c | 0 target/mips/{ => tcg}/txx9_translate.c | 0 target/mips/tcg/user/meson.build | 3 + target/mips/tcg/user/tlb_helper.c | 64 ++ target/mips/translate.h | 7 +- tests/tcg/hexagon/Makefile.target | 6 + tests/tcg/hexagon/brev.c | 190 ++++ tests/tcg/hexagon/circ.c | 486 +++++++++++ tests/tcg/hexagon/fpstuff.c | 242 ++++++ tests/tcg/hexagon/load_align.c | 415 +++++++++ tests/tcg/hexagon/load_unpack.c | 474 ++++++++++ tests/tcg/hexagon/misc.c | 47 + tests/tcg/hexagon/multi_result.c | 282 ++++++ 92 files changed, 6171 insertions(+), 2835 deletions(-) delete mode 100644 target/hexagon/conv_emu.c delete mode 100644 target/hexagon/conv_emu.h create mode 100644 target/mips/fpu.c create mode 100644 target/mips/msa.c delete mode 100644 target/mips/op_helper.c rename target/mips/{ => sysemu}/addr.c (100%) create mode 100644 target/mips/sysemu/cp0.c rename target/mips/{ => sysemu}/cp0_timer.c (100%) rename target/mips/{ => sysemu}/machine.c (94%) create mode 100644 target/mips/sysemu/meson.build create mode 100644 target/mips/sysemu/physaddr.c rename target/mips/{ => tcg}/dsp_helper.c (100%) create mode 100644 target/mips/tcg/exception.c rename target/mips/{ => tcg}/fpu_helper.c (99%) create mode 100644 target/mips/tcg/ldst_helper.c rename target/mips/{ => tcg}/lmmi_helper.c (100%) copy target/mips/{ => tcg}/meson.build (50%) rename target/mips/{ => tcg}/mips32r6.decode (100%) rename target/mips/{ => tcg}/mips64r6.decode (100%) rename target/mips/{ => tcg}/msa32.decode (100%) rename target/mips/{ => tcg}/msa64.decode (100%) rename target/mips/{ => tcg}/msa_helper.c (99%) rename target/mips/{ => tcg}/msa_helper.h.inc (100%) rename target/mips/{ => tcg}/msa_translate.c (100%) rename target/mips/{ => tcg}/mxu_translate.c (100%) create mode 100644 target/mips/tcg/op_helper.c rename target/mips/{ => tcg}/rel6_translate.c (100%) rename target/mips/{ => tcg/sysemu}/cp0_helper.c (100%) create mode 100644 target/mips/tcg/sysemu/meson.build rename target/mips/{ => tcg/sysemu}/mips-semi.c (100%) create mode 100644 target/mips/tcg/sysemu/special_helper.c rename target/mips/{ => tcg/sysemu}/tlb_helper.c (76%) create mode 100644 target/mips/tcg/sysemu_helper.h.inc create mode 100644 target/mips/tcg/tcg-internal.h rename target/mips/{ => tcg}/translate.c (99%) rename target/mips/{ => tcg}/translate_addr_const.c (100%) rename target/mips/{ => tcg}/tx79.decode (100%) rename target/mips/{ => tcg}/tx79_translate.c (100%) rename target/mips/{ => tcg}/txx9_translate.c (100%) create mode 100644 target/mips/tcg/user/meson.build create mode 100644 target/mips/tcg/user/tlb_helper.c create mode 100644 tests/tcg/hexagon/brev.c create mode 100644 tests/tcg/hexagon/circ.c create mode 100644 tests/tcg/hexagon/load_align.c create mode 100644 tests/tcg/hexagon/load_unpack.c create mode 100644 tests/tcg/hexagon/multi_result.c