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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allnoconfig in repository toolchain/ci/llvm-monorepo.
from d57abdac186 [PowerPC] Complete the custom legalization of vector int to [...] adds 645d02b4846 [PowerPC][NFC] Macro for register set defs for the Asm Parser adds 30ffad93013 [CodeGen] Replace '@' characters in block descriptors' symb [...] adds 8cac4ec796c [X86] Add custom type legalization for SIGN_EXTEND_VECTOR_I [...] adds 72c2927e891 [X86] Don't mark SEXTLOAD from v4i8/v4i16/v8i8 as Custom on [...] adds e222fdea47b [test] Remove flakiness decorator from TestObjCDynamicSBType adds 4ef2450ad58 [PowerPC] Fix ADDE, SUBE do not know how to promote operator adds 649be5807e4 [NFC] Fixed extra semicolon warning -This line, and those b [...]
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Summary of changes: clang/lib/CodeGen/CGBlocks.cpp | 3 + clang/test/CodeGenObjC/block-desc-str.m | 14 + clang/test/CodeGenObjCXX/block-nested-in-lambda.mm | 4 +- .../call-function/TestCallStopAndContinue.py | 2 - .../CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 5 + llvm/lib/Support/Error.cpp | 2 +- llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp | 165 +---- .../PowerPC/Disassembler/PPCDisassembler.cpp | 209 +------ .../Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h | 60 ++ llvm/lib/Target/X86/X86ISelLowering.cpp | 55 +- llvm/test/CodeGen/PowerPC/pr39815.ll | 31 + llvm/test/CodeGen/X86/madd.ll | 94 ++- llvm/test/CodeGen/X86/pmovsx-inreg.ll | 18 +- llvm/test/CodeGen/X86/pmul.ll | 106 ++-- llvm/test/CodeGen/X86/vec_cast.ll | 7 +- llvm/test/CodeGen/X86/vec_int_to_fp.ll | 27 +- llvm/test/CodeGen/X86/vector-sext.ll | 696 ++++++++------------- llvm/test/CodeGen/X86/vsel-cmp-load.ll | 14 +- 18 files changed, 570 insertions(+), 942 deletions(-) create mode 100644 clang/test/CodeGenObjC/block-desc-str.m create mode 100644 llvm/test/CodeGen/PowerPC/pr39815.ll