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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allmodconfig in repository toolchain/ci/llvm-project.
from 87210015581 gn build: Merge r355546 adds 8cedf04a6c8 Make ~mutex and ~condition_variable trivial on Windows. adds 842f55f3efe Process: generalise Windows thread setup adds 8d9d290d4c0 [ARM] Add support for MSVC stack cookie checking adds e28fca29fef Revert "[IRBuilder] Fold consistently for or/and whether co [...] adds 638b1a82d80 [NFC][PowerPC] Add the test add_cmp.ll adds 4cdb68ebbd5 [llvm-bcanalyzer] Refactor and move to libLLVMBitReader adds 46f2b583a2d [X86] Add MOVSDrr->MOVLPDrm entry to load folding table. Ad [...] adds 8f9e4d92e0d [clangd] Encapsulate fields in dex token. NFC adds d3bbc06ac79 [clangd] Avoid slow ostreams in URI conversion. adds f814dcbafba Make forward_list::remove/remove_if/unique all return void [...] adds e1e036a33bd [RISCV] Support z and i operand modifiers adds d8261f0288e [X86] Make movsd commutable to shufpd with a 0x02 immediate [...] adds 1deca50ab14 [X86] Allow execution domain fixing to turn SHUFPD into SHUFPS. adds 38902350ef4 [AMDGPU] Use a named predicate instead of a magic number. adds 23d10f7a4ed Change LaunchThread interface to return an Expected for non [...] adds 34958d12c9c [WebAssembly] Add static_assert(sizeof(SymbolUnion) <= 96) adds 1606a864647 [UpdateTestChecks] Skip over .Lfunc_begin for RISC-V adds 0464e07c8f6 [AArch64] Fix vsqadd scalar intrinsics operands adds 7d63be09b6a [ARM] Fix null pointer dereference in CodeGen/ARM/Windows/s [...] adds 4ec445b813a [AArch64] Fix scalar vuqadd intrinsics operands adds 0b9addb8c0c [RISCV] Specify registers used in DWARF exception handling adds d11df93898a [ubsan][test] Don't disable ubsan testing on 64-bit Solaris/x86 adds 04ea772d5af [ubsan][test] Fix several UBSan-* :: TestCases/ImplicitConv [...] adds d0e1d003971 [lld][WebAssembly] Fix typo in error message adds 77d4a8f9f7c [RISCV] Specify registers used for exception handling adds ee81051fc96 [ARM] Relax constraints on operands of VQxDMLxDH instructions adds 1f7bd40f681 [ubsan][test] Fix cast-overflow.cpp and delete float-divide [...] adds 15006469bfc [lld][WebAssembly] Fix __start/__stop symbols when combinin [...] adds 9285bf0fb99 [TargetLowering] SimplifyDemandedBits - just call computeKn [...] adds 556ec990e97 [lld] Use -o /dev/null in test when output is not needed. adds 674d8a947c7 [clangd] Use xxhash instead of SHA1 for background index fi [...] adds 8cf99a11704 [docs][llvm-objcopy] Add description of binary input/output to doc adds 1602058c045 [lit] Parse command-line options from LIT_OPTS adds 0752d12c091 [analyzer] Add analyzer option to limit the number of imported TUs adds e73805f80ea [ASTImporter] Fix import of lambda in function param adds 870d9c61b06 [llvm-ar][test] Increase llvm-ar test coverage adds 0c5fe7a440a Revert [llvm-ar][test] Increase llvm-ar test coverage adds 1159fe3f6e0 Reapply [llvm-ar][test] Increase llvm-ar test coverage adds 214f67ece54 GlobalISel: Check address space when looking up iPTR size adds bd791b57f8d GlobalISel: widenScalar for G_BUILD_VECTOR adds 2eff0318c66 [AMDGPU][MC] Corrected parsing of FLAT offset modifier adds ec575f6e3e5 [MIPS GlobalISel] Register bank select for G_STORE. Select [...] adds aa699b20a00 [MIPS GlobalISel] Register bank select for G_LOAD. Select i64 load adds 771769be901 [Float2Int] Add support for unary FNeg to Float2Int adds 74cbaa37b66 [InstCombine] add tests for splat shuffles; NFC adds 945b9ec0693 [libc++] Take 2: Do not cleverly link against libc++abi jus [...] adds c5f552d7059 [Triple] Add isRISCV function adds e1a9b49d6b9 [X86] ISD::INSERT_SUBVECTOR - use uint64_t index. NFCI. adds ce674579ffb [RISCV][NFC] Make use of Triple::isRISCV adds 41a414cdaa8 [PowerPC][NFC]Update testcases using script. adds 4aa2873fdce [clangd] A code tweak to expand a macro adds 060921dee71 [OPENMP]Make __kmpc_push_tripcount thread safe. adds 320a28200f2 [InstCombine] fix typo in test; NFC adds a914888b495 [OPENMP]Add -Wunintialized to the erroneous tests for futur [...] adds b52a0c0cc88 [docs][llvm-readobj][llvm-readelf] Improve wording adds b4b21d807e4 Add, and infer, a nofree function attribute adds b152f9f392d [pstl] Use a different namespace for each backend adds 10c96cabc17 [lldb] [test] Update NetBSD XFAILs in test suite adds 472e5dda110 Teach the IRBuilder about fadd and friends. new d6fd354f3f1 [Bitcode][NFC] Remove unused variable from BitcodeAnalyzer new e6ba22542f2 Add nofree attribute to CodeGenOpenCL/convergent.cl test new 0b59103a73b [InstCombine] canonicalize insert+splat to/from element 0 o [...] new 079f77b5906 GlobalISel: Convert some build functions to using SrcOp/DstOp new 2734f5c89c3 [Host] Fix out-of-line definition of StartMonitoringChildProcess new 498687bff2b Add, and infer, a nofree function attribute new c862ea27b7a [NFC][pstl] Remove unused utility code new cef9d42157e [AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description. new 6afc666eb86 [llvm\test\Object] - An initial step to cleanup the test cases. new 430b0497e76 AMDGPU: Move waitcnt intrinsic to instruction definition pattern new 224d8cd987b AMDGPU: Remove mubuf specific PatFrags new 81db9f543ce [WebAssembly] tablegen: distinguish float/int immediate operands.
The 12 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: clang-tools-extra/clangd/SourceCode.cpp | 9 +- clang-tools-extra/clangd/SourceCode.h | 3 +- clang-tools-extra/clangd/URI.cpp | 31 +- clang-tools-extra/clangd/index/Background.cpp | 1 - clang-tools-extra/clangd/index/Background.h | 1 - .../clangd/index/BackgroundIndexStorage.cpp | 7 - clang-tools-extra/clangd/index/Serialization.cpp | 2 +- clang-tools-extra/clangd/index/dex/PostingList.h | 2 +- clang-tools-extra/clangd/index/dex/Token.h | 11 +- .../clangd/refactor/tweaks/CMakeLists.txt | 2 + .../clangd/refactor/tweaks/ExpandMacro.cpp | 136 ++ .../clangd/unittests/SerializationTests.cpp | 5 +- clang-tools-extra/clangd/unittests/TweakTests.cpp | 93 + clang/include/clang/Basic/arm_neon.td | 4 +- clang/include/clang/CrossTU/CrossTranslationUnit.h | 10 +- .../clang/StaticAnalyzer/Core/AnalyzerOptions.def | 8 + clang/include/clang/Tooling/Syntax/Tokens.h | 9 + clang/lib/AST/ASTImporter.cpp | 23 +- clang/lib/Basic/Targets/RISCV.h | 9 + clang/lib/CrossTU/CrossTranslationUnit.cpp | 19 +- clang/lib/Driver/ToolChains/Gnu.cpp | 6 +- clang/lib/Driver/ToolChains/Linux.cpp | 3 +- clang/test/Analysis/analyzer-config.c | 3 +- clang/test/Analysis/ctu-import-threshold.c | 5 + clang/test/CodeGen/aarch64-neon-intrinsics.c | 16 +- .../CodeGen/aarch64-neon-vsqadd-float-conversion.c | 49 + .../aarch64-neon-vuqadd-float-conversion-warning.c | 26 + clang/test/CodeGen/builtins-riscv.c | 10 + clang/test/CodeGenOpenCL/convergent.cl | 2 +- clang/test/OpenMP/allocate_allocator_messages.cpp | 4 +- clang/test/OpenMP/atomic_messages.c | 4 +- clang/test/OpenMP/atomic_messages.cpp | 4 +- clang/test/OpenMP/cancel_if_messages.cpp | 10 +- clang/test/OpenMP/cancel_messages.cpp | 4 +- clang/test/OpenMP/critical_messages.cpp | 4 +- clang/test/OpenMP/declare_reduction_messages.c | 4 +- clang/test/OpenMP/declare_reduction_messages.cpp | 12 +- clang/test/OpenMP/distribute_collapse_messages.cpp | 12 +- .../OpenMP/distribute_dist_schedule_messages.cpp | 11 +- .../OpenMP/distribute_firstprivate_messages.cpp | 12 +- .../distribute_parallel_for_collapse_messages.cpp | 12 +- .../distribute_parallel_for_copyin_messages.cpp | 4 +- .../distribute_parallel_for_default_messages.cpp | 4 +- ...tribute_parallel_for_dist_schedule_messages.cpp | 12 +- ...stribute_parallel_for_firstprivate_messages.cpp | 12 +- .../OpenMP/distribute_parallel_for_if_messages.cpp | 12 +- ...istribute_parallel_for_lastprivate_messages.cpp | 4 +- .../OpenMP/distribute_parallel_for_messages.cpp | 4 +- ...istribute_parallel_for_num_threads_messages.cpp | 12 +- .../distribute_parallel_for_private_messages.cpp | 4 +- .../distribute_parallel_for_proc_bind_messages.cpp | 4 +- .../distribute_parallel_for_reduction_messages.cpp | 20 +- .../distribute_parallel_for_schedule_messages.cpp | 10 +- .../distribute_parallel_for_shared_messages.cpp | 4 +- ...stribute_parallel_for_simd_aligned_messages.cpp | 4 +- ...tribute_parallel_for_simd_collapse_messages.cpp | 12 +- ...istribute_parallel_for_simd_copyin_messages.cpp | 6 +- ...stribute_parallel_for_simd_default_messages.cpp | 4 +- ...te_parallel_for_simd_dist_schedule_messages.cpp | 11 +- ...ute_parallel_for_simd_firstprivate_messages.cpp | 12 +- .../distribute_parallel_for_simd_if_messages.cpp | 12 +- ...bute_parallel_for_simd_lastprivate_messages.cpp | 12 +- ...istribute_parallel_for_simd_linear_messages.cpp | 4 +- .../distribute_parallel_for_simd_loop_messages.cpp | 4 +- .../distribute_parallel_for_simd_misc_messages.c | 4 +- ...bute_parallel_for_simd_num_threads_messages.cpp | 12 +- ...stribute_parallel_for_simd_private_messages.cpp | 4 +- ...ribute_parallel_for_simd_proc_bind_messages.cpp | 4 +- ...ribute_parallel_for_simd_reduction_messages.cpp | 20 +- ...stribute_parallel_for_simd_safelen_messages.cpp | 12 +- ...tribute_parallel_for_simd_schedule_messages.cpp | 10 +- ...istribute_parallel_for_simd_shared_messages.cpp | 12 +- ...stribute_parallel_for_simd_simdlen_messages.cpp | 10 +- clang/test/OpenMP/distribute_private_messages.cpp | 6 +- .../OpenMP/distribute_simd_aligned_messages.cpp | 4 +- .../OpenMP/distribute_simd_collapse_messages.cpp | 12 +- .../distribute_simd_dist_schedule_messages.cpp | 11 +- .../distribute_simd_firstprivate_messages.cpp | 12 +- .../distribute_simd_lastprivate_messages.cpp | 8 +- .../OpenMP/distribute_simd_linear_messages.cpp | 4 +- .../test/OpenMP/distribute_simd_loop_messages.cpp | 4 +- clang/test/OpenMP/distribute_simd_misc_messages.c | 4 +- .../OpenMP/distribute_simd_private_messages.cpp | 4 +- .../OpenMP/distribute_simd_reduction_messages.cpp | 19 +- .../OpenMP/distribute_simd_safelen_messages.cpp | 12 +- .../OpenMP/distribute_simd_simdlen_messages.cpp | 12 +- clang/test/OpenMP/flush_messages.cpp | 4 +- clang/test/OpenMP/for_collapse_messages.cpp | 14 +- clang/test/OpenMP/for_firstprivate_messages.cpp | 8 +- clang/test/OpenMP/for_lastprivate_messages.cpp | 12 +- clang/test/OpenMP/for_linear_messages.cpp | 12 +- clang/test/OpenMP/for_loop_messages.cpp | 4 +- clang/test/OpenMP/for_misc_messages.c | 4 +- clang/test/OpenMP/for_private_messages.cpp | 4 +- clang/test/OpenMP/for_reduction_messages.cpp | 22 +- clang/test/OpenMP/for_schedule_messages.cpp | 10 +- clang/test/OpenMP/for_simd_aligned_messages.cpp | 4 +- clang/test/OpenMP/for_simd_collapse_messages.cpp | 12 +- .../test/OpenMP/for_simd_firstprivate_messages.cpp | 4 +- .../test/OpenMP/for_simd_lastprivate_messages.cpp | 12 +- clang/test/OpenMP/for_simd_linear_messages.cpp | 11 +- clang/test/OpenMP/for_simd_loop_messages.cpp | 4 +- clang/test/OpenMP/for_simd_misc_messages.c | 4 +- clang/test/OpenMP/for_simd_private_messages.cpp | 4 +- clang/test/OpenMP/for_simd_reduction_messages.cpp | 20 +- clang/test/OpenMP/for_simd_safelen_messages.cpp | 12 +- clang/test/OpenMP/for_simd_schedule_messages.cpp | 10 +- clang/test/OpenMP/for_simd_simdlen_messages.cpp | 12 +- clang/test/OpenMP/master_messages.cpp | 4 +- clang/test/OpenMP/ordered_messages.cpp | 12 +- clang/test/OpenMP/parallel_copyin_messages.cpp | 4 +- clang/test/OpenMP/parallel_default_messages.cpp | 12 +- .../test/OpenMP/parallel_firstprivate_messages.cpp | 8 +- .../test/OpenMP/parallel_for_collapse_messages.cpp | 12 +- clang/test/OpenMP/parallel_for_copyin_messages.cpp | 4 +- .../test/OpenMP/parallel_for_default_messages.cpp | 4 +- .../OpenMP/parallel_for_firstprivate_messages.cpp | 8 +- clang/test/OpenMP/parallel_for_if_messages.cpp | 12 +- .../OpenMP/parallel_for_lastprivate_messages.cpp | 12 +- clang/test/OpenMP/parallel_for_linear_messages.cpp | 12 +- clang/test/OpenMP/parallel_for_loop_messages.cpp | 4 +- clang/test/OpenMP/parallel_for_messages.cpp | 4 +- clang/test/OpenMP/parallel_for_misc_messages.c | 4 +- .../OpenMP/parallel_for_num_threads_messages.cpp | 12 +- .../test/OpenMP/parallel_for_ordered_messages.cpp | 12 +- .../test/OpenMP/parallel_for_private_messages.cpp | 4 +- .../OpenMP/parallel_for_proc_bind_messages.cpp | 4 +- .../OpenMP/parallel_for_reduction_messages.cpp | 20 +- .../test/OpenMP/parallel_for_schedule_messages.cpp | 10 +- .../OpenMP/parallel_for_simd_aligned_messages.cpp | 4 +- .../OpenMP/parallel_for_simd_collapse_messages.cpp | 12 +- .../OpenMP/parallel_for_simd_copyin_messages.cpp | 4 +- .../OpenMP/parallel_for_simd_default_messages.cpp | 4 +- .../parallel_for_simd_firstprivate_messages.cpp | 12 +- .../test/OpenMP/parallel_for_simd_if_messages.cpp | 12 +- .../parallel_for_simd_lastprivate_messages.cpp | 12 +- .../OpenMP/parallel_for_simd_linear_messages.cpp | 14 +- .../OpenMP/parallel_for_simd_loop_messages.cpp | 4 +- clang/test/OpenMP/parallel_for_simd_messages.cpp | 4 +- .../test/OpenMP/parallel_for_simd_misc_messages.c | 4 +- .../parallel_for_simd_num_threads_messages.cpp | 12 +- .../OpenMP/parallel_for_simd_private_messages.cpp | 12 +- .../parallel_for_simd_proc_bind_messages.cpp | 4 +- .../parallel_for_simd_reduction_messages.cpp | 20 +- .../OpenMP/parallel_for_simd_safelen_messages.cpp | 12 +- .../OpenMP/parallel_for_simd_schedule_messages.cpp | 10 +- .../OpenMP/parallel_for_simd_simdlen_messages.cpp | 12 +- clang/test/OpenMP/parallel_if_messages.cpp | 10 +- clang/test/OpenMP/parallel_messages.cpp | 4 +- .../test/OpenMP/parallel_num_threads_messages.cpp | 10 +- clang/test/OpenMP/parallel_private_messages.cpp | 8 +- clang/test/OpenMP/parallel_proc_bind_messages.cpp | 4 +- clang/test/OpenMP/parallel_reduction_messages.cpp | 20 +- .../OpenMP/parallel_sections_copyin_messages.cpp | 4 +- .../OpenMP/parallel_sections_default_messages.cpp | 4 +- .../parallel_sections_firstprivate_messages.cpp | 12 +- .../test/OpenMP/parallel_sections_if_messages.cpp | 10 +- .../parallel_sections_lastprivate_messages.cpp | 4 +- clang/test/OpenMP/parallel_sections_messages.cpp | 4 +- .../test/OpenMP/parallel_sections_misc_messages.c | 4 +- .../parallel_sections_num_threads_messages.cpp | 10 +- .../OpenMP/parallel_sections_private_messages.cpp | 12 +- .../parallel_sections_proc_bind_messages.cpp | 4 +- .../parallel_sections_reduction_messages.cpp | 20 +- .../OpenMP/parallel_sections_shared_messages.cpp | 8 +- clang/test/OpenMP/parallel_shared_messages.cpp | 8 +- clang/test/OpenMP/requires_messages.cpp | 2 +- .../test/OpenMP/sections_firstprivate_messages.cpp | 12 +- .../test/OpenMP/sections_lastprivate_messages.cpp | 12 +- clang/test/OpenMP/sections_misc_messages.c | 4 +- clang/test/OpenMP/sections_private_messages.cpp | 4 +- clang/test/OpenMP/sections_reduction_messages.cpp | 20 +- clang/test/OpenMP/simd_aligned_messages.cpp | 4 +- clang/test/OpenMP/simd_collapse_messages.cpp | 12 +- clang/test/OpenMP/simd_lastprivate_messages.cpp | 4 +- clang/test/OpenMP/simd_linear_messages.cpp | 12 +- clang/test/OpenMP/simd_loop_messages.cpp | 8 +- clang/test/OpenMP/simd_misc_messages.c | 4 +- clang/test/OpenMP/simd_private_messages.cpp | 4 +- clang/test/OpenMP/simd_reduction_messages.cpp | 20 +- clang/test/OpenMP/simd_safelen_messages.cpp | 12 +- clang/test/OpenMP/simd_simdlen_messages.cpp | 12 +- clang/test/OpenMP/single_copyprivate_messages.cpp | 14 +- clang/test/OpenMP/single_firstprivate_messages.cpp | 12 +- clang/test/OpenMP/single_misc_messages.c | 4 +- clang/test/OpenMP/single_private_messages.cpp | 4 +- clang/test/OpenMP/target_data_device_messages.cpp | 8 +- clang/test/OpenMP/target_data_if_messages.cpp | 8 +- clang/test/OpenMP/target_data_messages.c | 4 +- .../OpenMP/target_data_use_device_ptr_messages.cpp | 4 +- clang/test/OpenMP/target_defaultmap_messages.cpp | 4 +- clang/test/OpenMP/target_depend_messages.cpp | 4 +- clang/test/OpenMP/target_device_messages.cpp | 7 +- .../OpenMP/target_enter_data_depend_messages.cpp | 4 +- .../OpenMP/target_enter_data_device_messages.cpp | 8 +- .../test/OpenMP/target_enter_data_if_messages.cpp | 8 +- clang/test/OpenMP/target_enter_data_map_messages.c | 8 +- .../OpenMP/target_enter_data_nowait_messages.cpp | 4 +- .../OpenMP/target_exit_data_depend_messages.cpp | 4 +- .../OpenMP/target_exit_data_device_messages.cpp | 8 +- clang/test/OpenMP/target_exit_data_if_messages.cpp | 8 +- clang/test/OpenMP/target_exit_data_map_messages.c | 8 +- .../OpenMP/target_exit_data_nowait_messages.cpp | 4 +- clang/test/OpenMP/target_firstprivate_messages.cpp | 14 +- clang/test/OpenMP/target_if_messages.cpp | 10 +- .../test/OpenMP/target_is_device_ptr_messages.cpp | 6 +- clang/test/OpenMP/target_map_messages.cpp | 8 +- clang/test/OpenMP/target_nowait_messages.cpp | 4 +- .../OpenMP/target_parallel_default_messages.cpp | 4 +- .../OpenMP/target_parallel_defaultmap_messages.cpp | 4 +- .../OpenMP/target_parallel_depend_messages.cpp | 4 +- .../OpenMP/target_parallel_device_messages.cpp | 7 +- .../target_parallel_firstprivate_messages.cpp | 8 +- .../target_parallel_for_collapse_messages.cpp | 12 +- .../target_parallel_for_default_messages.cpp | 4 +- .../target_parallel_for_defaultmap_messages.cpp | 4 +- .../OpenMP/target_parallel_for_depend_messages.cpp | 4 +- .../OpenMP/target_parallel_for_device_messages.cpp | 8 +- .../target_parallel_for_firstprivate_messages.cpp | 12 +- .../OpenMP/target_parallel_for_if_messages.cpp | 11 +- .../target_parallel_for_is_device_ptr_messages.cpp | 4 +- .../target_parallel_for_lastprivate_messages.cpp | 4 +- .../OpenMP/target_parallel_for_linear_messages.cpp | 12 +- .../OpenMP/target_parallel_for_loop_messages.cpp | 4 +- .../OpenMP/target_parallel_for_map_messages.cpp | 4 +- clang/test/OpenMP/target_parallel_for_messages.cpp | 4 +- .../OpenMP/target_parallel_for_misc_messages.c | 4 +- .../OpenMP/target_parallel_for_nowait_messages.cpp | 4 +- .../target_parallel_for_num_threads_messages.cpp | 12 +- .../target_parallel_for_ordered_messages.cpp | 12 +- .../target_parallel_for_private_messages.cpp | 12 +- .../target_parallel_for_proc_bind_messages.cpp | 4 +- .../target_parallel_for_reduction_messages.cpp | 20 +- .../target_parallel_for_schedule_messages.cpp | 10 +- .../target_parallel_for_simd_aligned_messages.cpp | 4 +- .../target_parallel_for_simd_collapse_messages.cpp | 12 +- .../target_parallel_for_simd_default_messages.cpp | 4 +- ...arget_parallel_for_simd_defaultmap_messages.cpp | 4 +- .../target_parallel_for_simd_depend_messages.cpp | 4 +- .../target_parallel_for_simd_device_messages.cpp | 8 +- ...get_parallel_for_simd_firstprivate_messages.cpp | 12 +- .../target_parallel_for_simd_if_messages.cpp | 12 +- ...et_parallel_for_simd_is_device_ptr_messages.cpp | 4 +- ...rget_parallel_for_simd_lastprivate_messages.cpp | 12 +- .../target_parallel_for_simd_linear_messages.cpp | 12 +- .../target_parallel_for_simd_loop_messages.cpp | 4 +- .../target_parallel_for_simd_map_messages.cpp | 12 +- .../OpenMP/target_parallel_for_simd_messages.cpp | 4 +- .../target_parallel_for_simd_misc_messages.c | 4 +- .../target_parallel_for_simd_nowait_messages.cpp | 4 +- ...rget_parallel_for_simd_num_threads_messages.cpp | 12 +- .../target_parallel_for_simd_ordered_messages.cpp | 12 +- .../target_parallel_for_simd_private_messages.cpp | 12 +- ...target_parallel_for_simd_proc_bind_messages.cpp | 4 +- ...target_parallel_for_simd_reduction_messages.cpp | 20 +- .../target_parallel_for_simd_safelen_messages.cpp | 12 +- .../target_parallel_for_simd_schedule_messages.cpp | 10 +- .../target_parallel_for_simd_simdlen_messages.cpp | 12 +- clang/test/OpenMP/target_parallel_if_messages.cpp | 10 +- .../target_parallel_is_device_ptr_messages.cpp | 4 +- clang/test/OpenMP/target_parallel_map_messages.cpp | 8 +- clang/test/OpenMP/target_parallel_messages.cpp | 2 +- .../OpenMP/target_parallel_nowait_messages.cpp | 4 +- .../target_parallel_num_threads_messages.cpp | 10 +- .../OpenMP/target_parallel_private_messages.cpp | 4 +- .../OpenMP/target_parallel_proc_bind_messages.cpp | 4 +- .../OpenMP/target_parallel_reduction_messages.cpp | 20 +- .../OpenMP/target_parallel_shared_messages.cpp | 8 +- clang/test/OpenMP/target_private_messages.cpp | 4 +- clang/test/OpenMP/target_reduction_messages.cpp | 20 +- clang/test/OpenMP/target_simd_aligned_messages.cpp | 4 +- .../test/OpenMP/target_simd_collapse_messages.cpp | 8 +- .../OpenMP/target_simd_defaultmap_messages.cpp | 6 +- clang/test/OpenMP/target_simd_depend_messages.cpp | 4 +- clang/test/OpenMP/target_simd_device_messages.cpp | 8 +- .../OpenMP/target_simd_firstprivate_messages.cpp | 12 +- clang/test/OpenMP/target_simd_if_messages.cpp | 11 +- .../OpenMP/target_simd_is_device_ptr_messages.cpp | 4 +- .../OpenMP/target_simd_lastprivate_messages.cpp | 4 +- clang/test/OpenMP/target_simd_linear_messages.cpp | 12 +- clang/test/OpenMP/target_simd_loop_messages.cpp | 4 +- clang/test/OpenMP/target_simd_map_messages.cpp | 4 +- clang/test/OpenMP/target_simd_messages.cpp | 4 +- clang/test/OpenMP/target_simd_misc_messages.c | 4 +- clang/test/OpenMP/target_simd_nowait_messages.cpp | 4 +- clang/test/OpenMP/target_simd_private_messages.cpp | 12 +- .../test/OpenMP/target_simd_reduction_messages.cpp | 20 +- clang/test/OpenMP/target_simd_safelen_messages.cpp | 12 +- clang/test/OpenMP/target_simd_simdlen_messages.cpp | 12 +- .../test/OpenMP/target_teams_default_messages.cpp | 4 +- .../OpenMP/target_teams_defaultmap_messages.cpp | 4 +- clang/test/OpenMP/target_teams_depend_messages.cpp | 4 +- clang/test/OpenMP/target_teams_device_messages.cpp | 7 +- .../target_teams_distribute_collapse_messages.cpp | 12 +- .../target_teams_distribute_default_messages.cpp | 4 +- ...target_teams_distribute_defaultmap_messages.cpp | 4 +- .../target_teams_distribute_depend_messages.cpp | 4 +- .../target_teams_distribute_device_messages.cpp | 8 +- ...get_teams_distribute_dist_schedule_messages.cpp | 11 +- ...rget_teams_distribute_firstprivate_messages.cpp | 8 +- .../OpenMP/target_teams_distribute_if_messages.cpp | 11 +- ...arget_teams_distribute_lastprivate_messages.cpp | 4 +- .../target_teams_distribute_loop_messages.cpp | 4 +- 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llvm/docs/AMDGPU/gfx7_ssrc64_2.rst | 2 +- .../{gfx7_ssrc32_1.rst => gfx7_vsrc32_1.rst} | 6 +- llvm/docs/AMDGPU/gfx8_offset_buf.rst | 2 +- llvm/docs/AMDGPU/gfx8_src32_0.rst | 2 +- llvm/docs/AMDGPU/gfx8_src32_1.rst | 2 +- .../AMDGPU/{gfx8_src32_0.rst => gfx8_src32_2.rst} | 4 +- .../AMDGPU/{gfx8_src32_0.rst => gfx8_src32_3.rst} | 4 +- llvm/docs/AMDGPU/gfx8_src64_0.rst | 2 +- llvm/docs/AMDGPU/gfx8_src64_1.rst | 2 +- llvm/docs/AMDGPU/gfx8_ssrc32_0.rst | 2 +- llvm/docs/AMDGPU/gfx8_ssrc32_4.rst | 2 +- llvm/docs/AMDGPU/gfx8_ssrc64_0.rst | 2 +- llvm/docs/AMDGPU/gfx8_ssrc64_2.rst | 2 +- .../{gfx7_ssrc32_1.rst => gfx8_vsrc32_1.rst} | 6 +- llvm/docs/AMDGPU/gfx9_msg.rst | 1 + llvm/docs/AMDGPU/gfx9_offset_buf.rst | 2 +- llvm/docs/AMDGPU/gfx9_src32_0.rst | 2 +- llvm/docs/AMDGPU/gfx9_src32_1.rst | 2 +- .../AMDGPU/{gfx9_src32_0.rst => gfx9_src32_2.rst} | 4 +- .../AMDGPU/{gfx9_src32_0.rst => gfx9_src32_3.rst} | 4 +- llvm/docs/AMDGPU/gfx9_src64_0.rst | 2 +- llvm/docs/AMDGPU/gfx9_src64_1.rst | 2 +- llvm/docs/AMDGPU/gfx9_ssrc32_0.rst | 2 +- llvm/docs/AMDGPU/gfx9_ssrc32_4.rst | 2 +- llvm/docs/AMDGPU/gfx9_ssrc64_0.rst | 2 +- llvm/docs/AMDGPU/gfx9_ssrc64_2.rst | 2 +- .../{gfx7_ssrc32_1.rst => gfx9_vsrc32_1.rst} | 6 +- llvm/docs/AMDGPUInstructionSyntax.rst | 2 + llvm/docs/AMDGPUModifierSyntax.rst | 349 +++- llvm/docs/AMDGPUOperandSyntax.rst | 113 +- llvm/docs/AMDGPUUsage.rst | 7 +- llvm/docs/CommandGuide/lit.rst | 5 + llvm/docs/CommandGuide/llvm-objcopy.rst | 19 +- llvm/docs/CommandGuide/llvm-readelf.rst | 4 +- llvm/docs/CommandGuide/llvm-readobj.rst | 4 +- llvm/docs/LangRef.rst | 8 + llvm/include/llvm/ADT/Triple.h | 5 + llvm/include/llvm/Analysis/MemoryBuiltins.h | 13 + llvm/include/llvm/Analysis/TargetLibraryInfo.def | 9 + llvm/include/llvm/Bitcode/BitcodeAnalyzer.h | 103 + llvm/include/llvm/Bitcode/LLVMBitCodes.h | 1 + .../CodeGen/GlobalISel/InstructionSelectorImpl.h | 8 +- .../llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 19 +- llvm/include/llvm/IR/Attributes.td | 3 + llvm/include/llvm/IR/Function.h | 8 + llvm/include/llvm/IR/IRBuilder.h | 136 +- llvm/include/llvm/IR/IntrinsicInst.h | 49 +- llvm/lib/Analysis/MemoryBuiltins.cpp | 55 +- llvm/lib/AsmParser/LLLexer.cpp | 1 + llvm/lib/AsmParser/LLParser.cpp | 1 + llvm/lib/AsmParser/LLToken.h | 1 + .../Bitcode/Reader/BitcodeAnalyzer.cpp} | 1049 +++++----- llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 4 + llvm/lib/Bitcode/Reader/CMakeLists.txt | 1 + llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 2 + llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 19 + llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 97 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 26 +- llvm/lib/IR/Attributes.cpp | 2 + llvm/lib/IR/IntrinsicInst.cpp | 67 +- llvm/lib/IR/Verifier.cpp | 5 +- llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp | 14 +- llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp | 7 +- .../Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 108 +- llvm/lib/Target/AMDGPU/BUFInstructions.td | 40 +- llvm/lib/Target/AMDGPU/FLATInstructions.td | 50 +- .../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 31 +- .../Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h | 6 +- llvm/lib/Target/AMDGPU/SIInstrInfo.td | 14 +- llvm/lib/Target/AMDGPU/SOPInstructions.td | 14 +- llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 2 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 44 +- llvm/lib/Target/ARM/ARMISelLowering.h | 4 + llvm/lib/Target/ARM/ARMInstrMVE.td | 13 +- llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 10 +- llvm/lib/Target/Mips/MipsCallLowering.cpp | 4 +- llvm/lib/Target/Mips/MipsLegalizerInfo.cpp | 7 + llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp | 353 +++- llvm/lib/Target/Mips/MipsRegisterBankInfo.h | 81 + llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 36 +- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 10 + llvm/lib/Target/RISCV/RISCVISelLowering.h | 10 + .../WebAssembly/AsmParser/WebAssemblyAsmParser.cpp | 17 +- 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| 100 + .../Mips/GlobalISel/regbankselect/store.mir | 100 + llvm/test/CodeGen/PowerPC/add_cmp.ll | 76 + .../CodeGen/PowerPC/power9-moves-and-splats.ll | 46 +- .../CodeGen/RISCV/exception-pointer-register.ll | 130 ++ llvm/test/CodeGen/RISCV/inline-asm.ll | 45 + llvm/test/CodeGen/X86/buildvec-insertvec.ll | 4 +- llvm/test/CodeGen/X86/coalesce_commute_movsd.ll | 3 +- llvm/test/CodeGen/X86/combine-sdiv.ll | 75 +- llvm/test/CodeGen/X86/no-plt-libcalls.ll | 2 +- llvm/test/CodeGen/X86/palignr.ll | 8 +- llvm/test/CodeGen/X86/psubus.ll | 65 +- llvm/test/CodeGen/X86/sdiv-exact.ll | 17 +- llvm/test/CodeGen/X86/sse-align-12.ll | 4 +- llvm/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll | 28 +- llvm/test/CodeGen/X86/sse2.ll | 5 +- llvm/test/CodeGen/X86/swizzle-2.ll | 4 +- llvm/test/CodeGen/X86/trunc-subvector.ll | 6 +- llvm/test/CodeGen/X86/vector-blend.ll | 60 +- llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll | 44 +- llvm/test/CodeGen/X86/vector-shuffle-128-v2.ll | 77 +- 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llvm/test/tools/llvm-ar/symtab.test | 70 + llvm/test/tools/llvm-readobj/elf-no-action.test | 50 + llvm/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp | 1035 +--------- llvm/unittests/ADT/TripleTest.cpp | 2 + .../CodeGen/GlobalISel/LegalizerHelperTest.cpp | 47 + llvm/unittests/IR/IRBuilderTest.cpp | 64 + llvm/utils/UpdateTestChecks/asm.py | 2 +- llvm/utils/lit/lit/main.py | 4 +- llvm/utils/lit/tests/Inputs/lit-opts/lit.cfg | 7 + llvm/utils/lit/tests/Inputs/lit-opts/test.txt | 1 + llvm/utils/lit/tests/lit-opts.py | 33 + .../deviceRTLs/nvptx/test/parallel/tripcount.c | 22 + openmp/libomptarget/src/device.h | 6 +- openmp/libomptarget/src/interface.cpp | 7 +- openmp/libomptarget/src/omptarget.cpp | 8 +- openmp/libomptarget/src/private.h | 1 + pstl/include/pstl/internal/algorithm_impl.h | 4 +- pstl/include/pstl/internal/parallel_backend.h | 8 + .../pstl/internal/parallel_backend_serial.h | 12 +- pstl/include/pstl/internal/parallel_backend_tbb.h | 14 +- .../include/pstl/internal/parallel_backend_utils.h | 89 +- 893 files changed, 13877 insertions(+), 7966 deletions(-) create mode 100644 clang-tools-extra/clangd/refactor/tweaks/ExpandMacro.cpp create mode 100644 clang/test/Analysis/ctu-import-threshold.c create mode 100644 clang/test/CodeGen/aarch64-neon-vsqadd-float-conversion.c create mode 100644 clang/test/CodeGen/aarch64-neon-vuqadd-float-conversion-warning.c create mode 100644 clang/test/CodeGen/builtins-riscv.c create mode 100644 libcxx/src/condition_variable_destructor.cpp create mode 100644 lld/test/wasm/Inputs/explicit-section.ll create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst create mode 100644 llvm/docs/AMDGPU/gfx10_addr_buf.rst copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_addr_ds.rst} (55%) copy llvm/docs/AMDGPU/{gfx7_ssrc64_2.rst => gfx10_addr_flat.rst} (54%) create mode 100644 llvm/docs/AMDGPU/gfx10_addr_mimg.rst create mode 100644 llvm/docs/AMDGPU/gfx10_attr.rst copy llvm/docs/AMDGPU/{gfx7_ssrc64_2.rst => gfx10_base_smem_addr.rst} (54%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_base_smem_buf.rst} (52%) copy llvm/docs/AMDGPU/{gfx7_ssrc64_2.rst => gfx10_base_smem_scratch.rst} (54%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_bimm16.rst} (52%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_bimm32.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx10_data_buf_atomic128.rst create mode 100644 llvm/docs/AMDGPU/gfx10_data_buf_atomic32.rst create mode 100644 llvm/docs/AMDGPU/gfx10_data_buf_atomic64.rst create mode 100644 llvm/docs/AMDGPU/gfx10_data_mimg_atomic_cmp.rst create mode 100644 llvm/docs/AMDGPU/gfx10_data_mimg_atomic_reg.rst copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_data_mimg_store.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx10_data_mimg_store_d16.rst copy llvm/docs/AMDGPU/{gfx7_src32_3.rst => gfx10_data_smem_atomic128.rst} (50%) create mode 100644 llvm/docs/AMDGPU/gfx10_data_smem_atomic32.rst copy llvm/docs/AMDGPU/{gfx7_ssrc64_0.rst => gfx10_data_smem_atomic64.rst} (51%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_dst_buf_128.rst} (52%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_dst_buf_32.rst} (52%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_dst_buf_64.rst} (52%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_dst_buf_96.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx10_dst_buf_lds.rst copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_dst_flat_atomic32.rst} (55%) copy llvm/docs/AMDGPU/{gfx7_ssrc64_2.rst => gfx10_dst_flat_atomic64.rst} (54%) create mode 100644 llvm/docs/AMDGPU/gfx10_dst_mimg_gather4.rst create mode 100644 llvm/docs/AMDGPU/gfx10_dst_mimg_regular.rst create mode 100644 llvm/docs/AMDGPU/gfx10_dst_mimg_regular_d16.rst copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_fimm16.rst} (52%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_fimm32.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx10_hwreg.rst create mode 100644 llvm/docs/AMDGPU/gfx10_label.rst copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_mad_type_dev.rst} (52%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_mod_dpp_sdwa_abs_neg.rst} (52%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_mod_sdwa_sext.rst} (52%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_mod_vop3_abs_neg.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_msg.rst => gfx10_msg.rst} (97%) copy llvm/docs/AMDGPU/{gfx8_offset_buf.rst => gfx10_offset_buf.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx10_offset_smem_buf.rst create mode 100644 llvm/docs/AMDGPU/gfx10_offset_smem_plain.rst copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_opt.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx10_param.rst create mode 100644 llvm/docs/AMDGPU/gfx10_perm_smem.rst copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_ret.rst} (52%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_rsrc_buf.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx10_rsrc_mimg.rst create mode 100644 llvm/docs/AMDGPU/gfx10_saddr_flat_global.rst create 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llvm/docs/AMDGPU/{gfx7_src32_0.rst => gfx10_src32_0.rst} (59%) copy llvm/docs/AMDGPU/{gfx7_src32_3.rst => gfx10_src32_1.rst} (53%) copy llvm/docs/AMDGPU/{gfx7_src32_0.rst => gfx10_src32_2.rst} (56%) copy llvm/docs/AMDGPU/{gfx7_src32_0.rst => gfx10_src32_3.rst} (55%) copy llvm/docs/AMDGPU/{gfx7_src64_0.rst => gfx10_src64_0.rst} (58%) create mode 100644 llvm/docs/AMDGPU/gfx10_src_exp.rst create mode 100644 llvm/docs/AMDGPU/gfx10_ssrc32_0.rst copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_ssrc32_1.rst} (59%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_ssrc32_2.rst} (59%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_0.rst => gfx10_ssrc32_3.rst} (52%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_ssrc32_4.rst} (59%) create mode 100644 llvm/docs/AMDGPU/gfx10_ssrc32_5.rst copy llvm/docs/AMDGPU/{gfx7_ssrc64_2.rst => gfx10_ssrc64_0.rst} (51%) copy llvm/docs/AMDGPU/{gfx7_ssrc64_2.rst => gfx10_ssrc64_1.rst} (58%) create mode 100644 llvm/docs/AMDGPU/gfx10_tgt.rst copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_type_dev.rst} (52%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_uimm16.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx10_vaddr_flat_global.rst create mode 100644 llvm/docs/AMDGPU/gfx10_vaddr_flat_scratch.rst copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_vcc_32.rst} (52%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_vdata128_0.rst} (56%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_vdata32_0.rst} (59%) copy llvm/docs/AMDGPU/{gfx7_ssrc64_2.rst => gfx10_vdata64_0.rst} (58%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_vdata96_0.rst} (56%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_vdst128_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_vdst32_0.rst} (55%) copy llvm/docs/AMDGPU/{gfx7_ssrc64_2.rst => gfx10_vdst64_0.rst} (54%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_vdst96_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_vsrc128_0.rst} (56%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_vsrc32_0.rst} (59%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_vsrc32_1.rst} (59%) copy llvm/docs/AMDGPU/{gfx7_ssrc64_2.rst => gfx10_vsrc64_0.rst} (58%) create mode 100644 llvm/docs/AMDGPU/gfx10_waitcnt.rst copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_wsdst.rst} (52%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_wssrc.rst} (57%) copy llvm/docs/AMDGPU/{gfx7_src32_3.rst => gfx7_src32_4.rst} (72%) copy llvm/docs/AMDGPU/{gfx7_src32_3.rst => gfx7_src32_5.rst} (72%) copy llvm/docs/AMDGPU/{gfx7_src32_0.rst => gfx7_src32_6.rst} (73%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_4.rst => gfx7_ssrc32_5.rst} (95%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_0.rst => gfx7_ssrc32_6.rst} (67%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx7_vsrc32_1.rst} (59%) copy llvm/docs/AMDGPU/{gfx8_src32_0.rst => gfx8_src32_2.rst} (73%) copy llvm/docs/AMDGPU/{gfx8_src32_0.rst => gfx8_src32_3.rst} (77%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx8_vsrc32_1.rst} (59%) copy llvm/docs/AMDGPU/{gfx9_src32_0.rst => gfx9_src32_2.rst} (73%) copy llvm/docs/AMDGPU/{gfx9_src32_0.rst => gfx9_src32_3.rst} (77%) copy llvm/docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx9_vsrc32_1.rst} (59%) create mode 100644 llvm/include/llvm/Bitcode/BitcodeAnalyzer.h copy llvm/{tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp => lib/Bitcode/Reader/Bitcode [...] create mode 100644 llvm/test/CodeGen/ARM/Windows/stack-protector-msvc.ll create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/load.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/store.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load.ll create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/store.ll create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir create mode 100644 llvm/test/CodeGen/PowerPC/add_cmp.ll create mode 100644 llvm/test/CodeGen/RISCV/exception-pointer-register.ll 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