This is an automated email from the git hooks/post-receive script.
unknown user pushed a change to branch master in repository llvm.
from 459280c Increase the size of the sigaltstack used by LLVM signal hand [...] new 6648973 MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it. new 0c7940e [libFuzzer] use __attribute__((target("popcnt"))) only on x86_64
The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: include/llvm/CodeGen/MIRYamlMapping.h | 2 -- lib/CodeGen/MIRParser/MIRParser.cpp | 21 +++++++++--- lib/CodeGen/MIRPrinter.cpp | 1 - lib/CodeGen/MachineVerifier.cpp | 3 +- lib/Fuzzer/CMakeLists.txt | 2 +- lib/Fuzzer/FuzzerInternal.h | 14 +++++--- lib/Fuzzer/FuzzerTraceState.cpp | 2 +- lib/Fuzzer/FuzzerValueBitMap.h | 2 +- .../AArch64/GlobalISel/arm64-instructionselect.mir | 38 ---------------------- .../AArch64/GlobalISel/arm64-regbankselect.mir | 13 -------- test/CodeGen/AArch64/GlobalISel/legalize-add.mir | 3 -- test/CodeGen/AArch64/GlobalISel/legalize-and.mir | 1 - test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir | 1 - .../AArch64/GlobalISel/legalize-constant.mir | 2 -- .../GlobalISel/legalize-ignore-non-generic.mir | 2 -- .../AArch64/GlobalISel/legalize-load-store.mir | 2 -- test/CodeGen/AArch64/GlobalISel/legalize-mul.mir | 1 - test/CodeGen/AArch64/GlobalISel/legalize-or.mir | 1 - .../AArch64/GlobalISel/legalize-property.mir | 2 -- .../CodeGen/AArch64/GlobalISel/legalize-simple.mir | 1 - test/CodeGen/AArch64/GlobalISel/legalize-sub.mir | 1 - test/CodeGen/AArch64/GlobalISel/legalize-xor.mir | 1 - .../AArch64/GlobalISel/verify-regbankselected.mir | 1 - .../CodeGen/AArch64/GlobalISel/verify-selected.mir | 1 - test/CodeGen/AArch64/ldst-opt-dbg-limit.mir | 2 -- test/CodeGen/AArch64/movimm-wzr.mir | 1 - test/CodeGen/AMDGPU/detect-dead-lanes.mir | 9 ----- test/CodeGen/ARM/ARMLoadStoreDBG.mir | 1 - .../AArch64/generic-virtual-registers-error.mir | 1 - ...eneric-virtual-registers-with-regbank-error.mir | 1 - .../MIR/AArch64/inst-size-tlsdesc-callseq.mir | 1 - test/CodeGen/MIR/AArch64/machine-scheduler.mir | 1 - .../MIR/AArch64/stack-object-local-offset.mir | 1 - test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir | 1 - test/CodeGen/MIR/Generic/frame-info.mir | 2 -- test/CodeGen/MIR/Generic/register-info.mir | 7 ++-- test/CodeGen/MIR/Lanai/peephole-compare.mir | 9 ----- .../MIR/PowerPC/unordered-implicit-registers.mir | 1 - ...expected-metadata-node-after-debug-location.mir | 1 - .../X86/expected-metadata-node-after-exclaim.mir | 1 - ...expected-named-register-in-functions-livein.mir | 1 - .../MIR/X86/expected-subregister-after-colon.mir | 1 - ...pected-virtual-register-in-functions-livein.mir | 1 - test/CodeGen/MIR/X86/function-liveins.mir | 1 - test/CodeGen/MIR/X86/generic-instr-type.mir | 2 -- .../MIR/X86/instructions-debug-location.mir | 2 -- .../CodeGen/MIR/X86/invalid-metadata-node-type.mir | 1 - test/CodeGen/MIR/X86/metadata-operands.mir | 1 - test/CodeGen/MIR/X86/stack-object-debug-info.mir | 1 - .../stack-object-operand-name-mismatch-error.mir | 1 - test/CodeGen/MIR/X86/stack-object-operands.mir | 1 - test/CodeGen/MIR/X86/standalone-register-error.mir | 1 - .../CodeGen/MIR/X86/subregister-index-operands.mir | 1 - test/CodeGen/MIR/X86/subregister-operands.mir | 1 - .../MIR/X86/undefined-fixed-stack-object.mir | 1 - test/CodeGen/MIR/X86/undefined-register-class.mir | 1 - test/CodeGen/MIR/X86/undefined-stack-object.mir | 1 - .../CodeGen/MIR/X86/undefined-virtual-register.mir | 1 - .../unexpected-size-non-generic-register-phys.mir | 1 - .../X86/unexpected-size-non-generic-register.mir | 1 - test/CodeGen/MIR/X86/unknown-metadata-node.mir | 1 - .../MIR/X86/unknown-subregister-index-op.mir | 1 - test/CodeGen/MIR/X86/unknown-subregister-index.mir | 1 - .../X86/virtual-register-redefinition-error.mir | 1 - test/CodeGen/MIR/X86/virtual-registers.mir | 2 -- test/CodeGen/PowerPC/aantidep-def-ec.mir | 1 - test/CodeGen/PowerPC/addisdtprelha-nonr3.mir | 1 - test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir | 1 - test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir | 1 - test/CodeGen/X86/eflags-copy-expansion.mir | 1 - test/CodeGen/X86/fixup-bw-copy.mir | 7 ---- test/CodeGen/X86/implicit-null-checks.mir | 1 - .../DebugInfo/MIR/X86/live-debug-values-3preds.mir | 1 - test/DebugInfo/MIR/X86/live-debug-values.mir | 1 - 74 files changed, 34 insertions(+), 167 deletions(-)