This is an automated email from the git hooks/post-receive script.
tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/qemu.
from f228336020 Merge tag 'pull-target-arm-20220428' of https://git.linaro.o [...] adds 6d3b9c024c hw/riscv: spike: Add '/chosen/stdout-path' in device tree un [...] adds 58303fc0be hw/riscv: Don't add empty bootargs to device tree adds 9951ba948a target/riscv: Support configuarable marchid, mvendorid, mipi [...] adds eef82872be target/riscv: rvk: add cfg properties for zbk* and zk* adds d8e81e3c18 target/riscv: rvk: add support for zbkb extension adds 5cc69ceb68 target/riscv: rvk: add support for zbkc extension adds 0496389680 target/riscv: rvk: add support for zbkx extension adds c29da5a7fe crypto: move sm4_sbox from target/arm adds 68d19b58f4 target/riscv: rvk: add support for zknd/zkne extension in RV32 adds 9e33e1753b target/riscv: rvk: add support for zkne/zknd extension in RV64 adds 387e5d9271 target/riscv: rvk: add support for sha256 related instructio [...] adds e9a7ef5d5e target/riscv: rvk: add support for sha512 related instructio [...] adds 1f7f7b5ede target/riscv: rvk: add support for sha512 related instructio [...] adds 0976083d1b target/riscv: rvk: add support for zksed/zksh extension adds 77442380ec target/riscv: rvk: add CSR support for Zkr adds 5748c886b1 disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions adds cf7ed971ae target/riscv: rvk: expose zbk* and zk* properties adds 457a86a0eb target/riscv: Fix incorrect PTE merge in walk_pte adds a62c2c155c target/riscv: add scalar crypto related extenstion strings t [...] adds 1c20d3ff60 hw/riscv: virt: Add a machine done notifier adds d24a7bc24e hw/core: Move the ARM sysbus-fdt to core adds 1832b7cb3f hw/riscv: virt: Create a platform bus adds 3029fab643 hw/riscv: virt: Add support for generating platform FDT entries adds 58d5a5a78c hw/riscv: virt: Add device plug support adds 325b7c4e75 hw/riscv: Enable TPM backends adds 731340813f Merge tag 'pull-riscv-to-apply-20220429' of github.com:alist [...]
No new revisions were added by this update.
Summary of changes: crypto/meson.build | 1 + crypto/sm4.c | 49 ++++ disas/riscv.c | 173 +++++++++++++- docs/system/riscv/virt.rst | 20 ++ hw/arm/meson.build | 1 - hw/arm/virt.c | 2 +- hw/arm/xlnx-versal-virt.c | 1 - hw/core/meson.build | 1 + hw/{arm => core}/sysbus-fdt.c | 2 +- hw/riscv/Kconfig | 2 + hw/riscv/microchip_pfsoc.c | 2 +- hw/riscv/sifive_u.c | 2 +- hw/riscv/spike.c | 7 +- hw/riscv/virt.c | 319 +++++++++++++++++--------- include/crypto/sm4.h | 6 + include/hw/{arm => core}/sysbus-fdt.h | 0 include/hw/riscv/virt.h | 8 +- target/arm/crypto_helper.c | 36 +-- target/riscv/bitmanip_helper.c | 80 +++++++ target/riscv/cpu.c | 58 +++++ target/riscv/cpu.h | 17 ++ target/riscv/cpu_bits.h | 9 + target/riscv/crypto_helper.c | 302 ++++++++++++++++++++++++ target/riscv/csr.c | 118 +++++++++- target/riscv/helper.h | 22 ++ target/riscv/insn32.decode | 97 ++++++-- target/riscv/insn_trans/trans_rvb.c.inc | 116 ++++++++-- target/riscv/insn_trans/trans_rvk.c.inc | 391 ++++++++++++++++++++++++++++++++ target/riscv/meson.build | 3 +- target/riscv/monitor.c | 11 +- target/riscv/op_helper.c | 9 + target/riscv/pmp.h | 8 +- target/riscv/translate.c | 8 + 33 files changed, 1682 insertions(+), 199 deletions(-) create mode 100644 crypto/sm4.c rename hw/{arm => core}/sysbus-fdt.c (99%) create mode 100644 include/crypto/sm4.h rename include/hw/{arm => core}/sysbus-fdt.h (100%) create mode 100644 target/riscv/crypto_helper.c create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc