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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-defconfig in repository toolchain/ci/llvm-project.
from f7a26127f21 [clangd] Release notes for b8c37153d5393aad96 adds a781a706b96 [WebAssembly][SIMD] Rename shuffle, swizzle, and load_splats adds 8de43b926f0 [mlir] Remove instance methods from LLVMType adds 1c19804ebf4 [OpenMP] Add OpenMP Documentation for Libomptarget environm [...] adds 75a3f326c3d [IR] Add an ImplicitLocOpBuilder helper class for building [...] adds 6dfe5801e01 scudo: Move the configuration for the primary allocator to [...] adds ca4bf58e4ee [AMDGPU] Support unaligned flat scratch in TLI adds d15119a02d9 [AMDGPU][GlobalISel] GlobalISel for flat scratch adds e6b3db6309f scudo: Replace the Cache argument on MapAllocator with a Co [...] adds faac1c02c80 scudo: Move the management of the UseMemoryTagging bit out [...] adds 22cf54a7fba Replace `T(x)` with `reinterpret_cast<T>(x)` everywhere it [...] adds 5bec0828347 VirtRegMap: Use Register adds 29ed846d671 AMDGPU: Fix assert when checking for implicit operand legality adds c8874464b5f [RISCV] Add intrinsics for vslide1up/down, vfslide1up/down [...] adds 42687839980 [RISCV] Add intrinsics for vwmacc[u|su|us] instructions adds ad0a7ad950f [RISCV] Add intrinsics for vf[n]macc/vf[n]msac/vf[n]madd/vf [...] adds bac54639c7b AMDGPU: Add spilled CSR SGPRs to entry block live ins adds 8bf9cdeaee4 AMDGPU: Use Register adds 77fb45e59e4 [lld/mac] Add --version flag adds 581d13f8aeb GlobalISel: Return APInt from getConstantVRegVal new e6fde1ae7df [MemorySSA] Use is_contained (NFC) new efe7f5ede0b [WebAssembly][NFC] Refactor SIMD load/store tablegen defs new 3c707d73f26 [NewGVN] Remove for_each_found (NFC)
The 3 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: clang/lib/CodeGen/CGCall.h | 6 +- .../lib/scudo/standalone/allocator_config.h | 51 +- compiler-rt/lib/scudo/standalone/combined.h | 32 +- compiler-rt/lib/scudo/standalone/memtag.h | 5 + compiler-rt/lib/scudo/standalone/options.h | 6 + compiler-rt/lib/scudo/standalone/primary32.h | 32 +- compiler-rt/lib/scudo/standalone/primary64.h | 35 +- compiler-rt/lib/scudo/standalone/secondary.h | 14 +- .../lib/scudo/standalone/tests/combined_test.cpp | 25 +- .../lib/scudo/standalone/tests/primary_test.cpp | 62 +- .../lib/scudo/standalone/tests/secondary_test.cpp | 20 +- lld/COFF/Options.td | 2 +- lld/MachO/Driver.cpp | 7 +- lld/MachO/Options.td | 4 +- lld/test/MachO/driver.test | 4 +- .../llvm/CodeGen/GlobalISel/MIPatternMatch.h | 2 +- llvm/include/llvm/CodeGen/GlobalISel/Utils.h | 11 +- llvm/include/llvm/CodeGen/VirtRegMap.h | 8 +- llvm/include/llvm/IR/IntrinsicsRISCV.td | 38 +- llvm/include/llvm/IR/SymbolTableListTraits.h | 8 +- llvm/include/llvm/Object/Binary.h | 4 +- llvm/lib/Analysis/MemorySSA.cpp | 3 +- llvm/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp | 7 +- llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp | 28 +- .../lib/CodeGen/GlobalISel/InstructionSelector.cpp | 2 +- llvm/lib/CodeGen/GlobalISel/Utils.cpp | 30 +- llvm/lib/CodeGen/LiveRangeEdit.cpp | 2 +- llvm/lib/Object/COFFObjectFile.cpp | 24 +- llvm/lib/Object/ELFObjectFile.cpp | 3 +- llvm/lib/Object/XCOFFObjectFile.cpp | 4 +- .../AArch64/GISel/AArch64InstructionSelector.cpp | 47 +- .../Target/AArch64/GISel/AArch64LegalizerInfo.cpp | 2 +- .../AArch64/GISel/AArch64PostLegalizerCombiner.cpp | 2 +- .../AArch64/GISel/AArch64PostLegalizerLowering.cpp | 2 +- llvm/lib/Target/AMDGPU/AMDGPUGISel.td | 8 + .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 81 +- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 3 + llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 26 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 8 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 15 +- llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 19 +- llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp | 9 +- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 120 +- .../MCTargetDesc/WebAssemblyMCTargetDesc.h | 40 +- .../lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 322 +++-- llvm/lib/Target/X86/X86InstructionSelector.cpp | 2 +- llvm/lib/Transforms/Scalar/NewGVN.cpp | 12 - .../test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll | 759 +++++++++++ llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll | 11 +- .../CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir | 35 + llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir | 16 + llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll | 69 +- llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll | 856 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll | 1142 ++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll | 856 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll | 1142 ++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll | 856 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll | 1142 ++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll | 856 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll | 1142 ++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll | 856 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll | 1142 ++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll | 856 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll | 1142 ++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll | 856 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll | 1142 ++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll | 856 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll | 1142 ++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll | 512 +++++++ llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll | 698 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll | 523 ++++++++ llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll | 713 ++++++++++ llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll | 800 +++++++++++ llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll | 978 ++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll | 24 + llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll | 1000 ++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll | 1034 ++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll | 1412 ++++++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll | 1034 ++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll | 1412 ++++++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll | 1034 ++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll | 1412 ++++++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll | 516 +++++++ llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll | 704 ++++++++++ llvm/test/CodeGen/WebAssembly/simd-build-vector.ll | 6 +- llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll | 10 +- llvm/test/CodeGen/WebAssembly/simd-load-splat.ll | 2 +- .../WebAssembly/simd-load-store-alignment.ll | 36 +- .../CodeGen/WebAssembly/simd-nested-shuffles.ll | 2 +- llvm/test/CodeGen/WebAssembly/simd-offset.ll | 96 +- .../WebAssembly/simd-shift-complex-splats.ll | 2 +- .../CodeGen/WebAssembly/simd-shuffle-bitcast.ll | 2 +- llvm/test/CodeGen/WebAssembly/simd.ll | 48 +- llvm/test/MC/Disassembler/WebAssembly/wasm.txt | 2 +- llvm/test/MC/WebAssembly/simd-encodings.s | 24 +- .../AMDGPU/adjust-alloca-alignment.ll | 35 +- llvm/tools/llvm-readobj/ELFDumper.cpp | 12 +- .../StandardToLLVM/ConvertStandardToLLVM.h | 3 +- mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td | 28 +- mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h | 75 +- mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td | 9 +- mlir/include/mlir/IR/ImplicitLocOpBuilder.h | 123 ++ mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp | 102 +- .../GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp | 15 +- mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h | 18 +- .../Conversion/GPUCommon/OpToFuncCallLowering.h | 9 +- .../GPUToVulkan/ConvertLaunchFuncToVulkanCalls.cpp | 45 +- .../Conversion/SPIRVToLLVM/ConvertSPIRVToLLVM.cpp | 8 +- .../Conversion/StandardToLLVM/StandardToLLVM.cpp | 159 ++- .../VectorToLLVM/ConvertVectorToLLVM.cpp | 22 +- .../lib/Conversion/VectorToROCDL/VectorToROCDL.cpp | 6 +- mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp | 211 +-- mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp | 170 +-- mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp | 5 +- mlir/lib/ExecutionEngine/JitRunner.cpp | 19 +- mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp | 45 +- mlir/lib/Target/LLVMIR/ModuleTranslation.cpp | 4 +- mlir/test/Dialect/LLVMIR/invalid.mlir | 8 +- openmp/docs/design/Runtimes.rst | 82 ++ 120 files changed, 32205 insertions(+), 1117 deletions(-) create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll create mode 100644 llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll create mode 100644 mlir/include/mlir/IR/ImplicitLocOpBuilder.h