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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allyesconfig in repository toolchain/ci/llvm-project.
from e334c52addc [llvm-objcopy] Use llvm::erase_if (NFC) adds 622ea9cf74b [RISCV] Define vector widening reduction intrinsic. adds e8c7e7cdbbb [ValueTracking] Add more known non zero tests (NFC) adds b2184075127 [ValueTracking] Handle more non-trivial conditions in isKno [...] adds c7dcc4c7258 [clang-format] PR48569 clang-format fails to align case lab [...] adds c4ca1089669 [SLP] use switch to improve readability; NFC adds badf0f20f3b [SLP] rename reduction variables for readability; NFC adds 62beac7ed7c [NFC] Refactor some SourceMgr code new 9c9bca45f09 [llvm-pdbutil] Use llvm::is_contained (NFC) new 63a2bde2812 [TableGen] Use llvm::erase_if (NFC) new b676f2fee1f [llvm-cov, llvm-symbolizer] Use llvm::erase_if (NFC)
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Summary of changes: clang/lib/Format/UnwrappedLineParser.cpp | 19 ++- clang/unittests/Format/FormatTest.cpp | 14 +-- llvm/include/llvm/IR/IntrinsicsRISCV.td | 6 + llvm/lib/Analysis/ValueTracking.cpp | 2 +- llvm/lib/Support/SourceMgr.cpp | 28 ++--- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 40 +++++++ llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 127 ++++++++++----------- llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll | 43 +++++++ llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll | 85 ++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv32.ll | 43 +++++++ llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv64.ll | 85 ++++++++++++++ llvm/test/Transforms/IndVarSimplify/X86/pr45360.ll | 26 ++--- llvm/test/Transforms/InstCombine/known-non-zero.ll | 92 +++++++++++++++ llvm/tools/llvm-cov/CodeCoverage.cpp | 11 +- llvm/tools/llvm-pdbutil/llvm-pdbutil.cpp | 4 +- llvm/tools/llvm-symbolizer/llvm-symbolizer.cpp | 6 +- llvm/utils/TableGen/AsmWriterEmitter.cpp | 6 +- 17 files changed, 513 insertions(+), 124 deletions(-) create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv64.ll