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from a2b05bc24df CodeGen: Introduce a class for registers new a3af6bb71d9 GlobalISel: Remove unsigned variant of SrcOp new bc1fbc21839 ARC: Fix -Wimplicit-fallthrough new 8ae33d076e0 Hexagon: Rename another copy of Register class
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Summary of changes: include/llvm/CodeGen/CallingConvLower.h | 2 +- include/llvm/CodeGen/GlobalISel/CallLowering.h | 10 +- include/llvm/CodeGen/GlobalISel/CombinerHelper.h | 5 +- include/llvm/CodeGen/GlobalISel/IRTranslator.h | 8 +- include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 3 +- include/llvm/CodeGen/MachineInstrBuilder.h | 2 +- include/llvm/CodeGen/SwiftErrorValueTracking.h | 6 +- lib/CodeGen/GlobalISel/CallLowering.cpp | 2 +- lib/CodeGen/GlobalISel/CombinerHelper.cpp | 10 +- lib/CodeGen/GlobalISel/IRTranslator.cpp | 168 +++++++------- lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 254 ++++++++++----------- lib/CodeGen/SwiftErrorValueTracking.cpp | 18 +- lib/Target/AArch64/AArch64CallLowering.cpp | 32 +-- lib/Target/AArch64/AArch64InstructionSelector.cpp | 204 ++++++++--------- lib/Target/AMDGPU/AMDGPUCallLowering.cpp | 28 +-- lib/Target/AMDGPU/AMDGPUCallLowering.h | 2 +- lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 24 +- lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 4 +- lib/Target/ARC/ARCRegisterInfo.cpp | 4 + lib/Target/ARM/ARMCallLowering.cpp | 26 +-- lib/Target/ARM/ARMLegalizerInfo.cpp | 2 +- lib/Target/Hexagon/HexagonConstPropagation.cpp | 177 +++++++------- lib/Target/Mips/MipsCallLowering.cpp | 28 +-- lib/Target/Mips/MipsCallLowering.h | 2 +- lib/Target/Mips/MipsInstructionSelector.cpp | 43 ++-- lib/Target/Mips/MipsMachineFunction.cpp | 4 +- lib/Target/Mips/MipsMachineFunction.h | 4 +- lib/Target/X86/X86CallLowering.cpp | 22 +- lib/Target/X86/X86RegisterInfo.h | 6 +- unittests/CodeGen/GlobalISel/PatternMatchTest.cpp | 16 +- 30 files changed, 562 insertions(+), 554 deletions(-)