[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allyesconfig updated (1e23802507d -> 329b887286a)

30 Dec 2020


      This is an automated email from the git hooks/post-receive script.
tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allyesconfig
in repository toolchain/ci/llvm-project.
from  1e23802507d [IROutliner] Merging identical output blocks for extracted  [...]
      adds  1e3ed09165c [CodeGen] Use llvm::append_range (NFC)
      adds  5d2529f28f9 [Scalar] Construct SmallVector with iterator ranges (NFC)
      adds  2883cd98f3c [CFGPrinter] Use succ_empty (NFC)
      adds  55d13e6a867 [asan][test] Annotate glibc specific tests with REQUIRES: g [...]
      adds  c2ef06d3dd0 [NewPM] Port infer-address-spaces
      adds  c5d100fdf2d [test] Fix conditional-temporaries.cpp
      adds  a8970dff1ae [ubsan][test] FLush stdout before checking interleaved stdo [...]
      adds  53f80d6b3a0 [lldb] Fix logging in lldb-server tests
      adds  ed146d6291c [LLD][ELF] - Use LLVM_ELF_IMPORT_TYPES_ELFT instead of mult [...]
      adds  ae6e89327b0 Precommit tests that have poison as shufflevector's placeholder
      adds  a0b68a2925f [lldb] Deduplicate some tests in TestLldbGdbServer
      adds  5abfeccf10b [ARM][AArch64] Add Cortex-A78C Support for Clang and LLVM
      adds  0a19fc3088f [PowerPC] Disable CTR loops containing operations on half-p [...]
      adds  aebb4a60522 [RISCV] Rewrite and simplify helper function. NFC.
      adds  7486de1b2ec [PowerPC] Provide patterns for permuted scalar to vector fo [...]
      adds  374ef57f137 [InstCombine] 'hoist xor-by-constant from xor-by-value': co [...]
      adds  b76014a4f15 RegionInfo: use a range-based for loop [NFCI]
      adds  cf216670a0b [mlir][linalg] Add vectorization for linalg on tensor ops
      adds  c1e85b6c1b4 sanitizer: fix typo/spelling: Dissassemble → Disassemble
      adds  2ae760e27e6 [RISCV] Add earlyclobber of destination register to vmsbf.m [...]
      adds  b980bed34b9 [MSSAUpdater] Skip renaming when inserting def in unreachab [...]
      adds  7ecbe0c7a01 [NewPM][AMDGPU] Port amdgpu-lower-kernel-attributes
      adds  79cbb003c53 [RISCV] Don't use tail agnostic policy on instructions wher [...]
      adds  6df161a2fbf [IROutliner] Adding a cost model, and debug option to turn  [...]
      adds  278aa65cc49 [IR] Let IRBuilder's CreateVectorSplat/CreateShuffleVector  [...]
      adds  f7f09e2b1c8 [RISCV] Fill out basic integer RVV ISel patterns
      adds  21a3a0225d8 [SLP] replace local reduction enum with RecurrenceKind; NFCI
      adds  df7ddeea668 [mlir][python] Add FlatSymbolRef attribute.
      adds  8d18bc8e6db [Utils] reduce code in createTargetReduction(); NFC
      adds  145cbef5879 Copy demangle changes from libcxxabi to llvm with cp_to_llvm.sh.
      adds  6027e05dbfc [SimplifyCFG] Teach SimplifyEqualityComparisonWithOnlyPrede [...]
      adds  fe9bdd96215 [SimplifyCFG] Teach SimplifyEqualityComparisonWithOnlyPrede [...]
      adds  18c407bf4c1 [SimplifyCFG] Teach HoistThenElseCodeToIf() to preserve DomTree
      adds  b8121b2e62d [SimplifyCFG] Teach SinkCommonCodeFromPredecessors() to pre [...]
      adds  d4c0abb4a31 [SimplifyCFG] Teach FoldCondBranchOnPHI() to preserve DomTree
      adds  307156246f7 [SimplifyCFG] Teach mergeConditionalStoreToAddress() to pre [...]
      adds  ec0b671a614 [SimplifyCFG] Teach SimplifyCondBranchToCondBranch() to pre [...]
      adds  39a56f7f172 [SimplifyCFG] Teach SimplifyTerminatorOnSelect() to preserv [...]
      adds  df4a931c63b [IROutliner] Adding OptRemarks to the IROutliner Pass
      adds  e03266994af [mlir] Skip empty op-pipelines in inliner textual opt parsing
      adds  673b12e76ff [tsan] Remove stdlib.h from dd_interceptors.cpp
      adds  4e74480e023 [NFC][sanitizer] Simplify InternalLowerBound
      adds  ababeca34b3 [NFC][sanitizer] Add SortAndDedup function
      adds  3c0d36f977d [NFC][lsan] Add nested leak in test
      adds  f5665a24862 [mlir][python] Add Operation.verify().
      adds  14056c88d66 [mlir][Python] Add an Operation.name property
      adds  5fd2b3a1246 [mlir] Add error message when failing to add pass
      adds  7e5a187de31 CrashReason: Add MTE tag check faults to the list of crash  [...]
      adds  fddb4174495 [llvm-elfabi] Add flag to preserve timestamp when output is [...]
      adds  21314940c48 Reland "[NewPM][CodeGen] Introduce CodeGenPassBuilder to he [...]
      adds  92207b2ccea [gn build] Port 21314940c48
      adds  2c8f5bd5394 [MLIR] Make ComplexType buildable if its element type is buildable
      adds  58ce477676c Fix DRR pattern when attributes and operands are interleave [...]
      adds  16c8f6e9134 Revert "Reland "[NewPM][CodeGen] Introduce CodeGenPassBuild [...]
      adds  a373eacb567 [gn build] Port 16c8f6e9134
      adds  480936e741d Reland "[NewPM][CodeGen] Introduce CodeGenPassBuilder to he [...]
      adds  57b8afda10b [gn build] Port 480936e741d
      adds  6da00336248 [RISCV] Define vsext/vzext intrinsics.
      adds  d034a94e7b3 Revert "[llvm-elfabi] Add flag to preserve timestamp when o [...]
      adds  9a5261efd75 [lsan] Parse suppressions just before leak reporting
      adds  9b25b8068df [NFC][lsan] Extract PrintResults function
      adds  8a1f1a100cc [mlir][python] Aggressively avoid name collisions in genera [...]
      adds  5efc71e119d [ORC] Move Orc RPC code into Shared, rename some RPC types.
      adds  f904d50c29f [PowerPC] Remaining KnownBits should be constant when perfo [...]
      adds  e3e25cfb44b [PowerPC] Add mir test to show effect of `optimizeCompareIn [...]
       new  096b02ebbff [RISCV] Add intrinsics for vcompress instruction
       new  f76e83bfbba [Analysis] Use llvm::append_range (NFC)
       new  16d20e2554e [Transforms/Utils] Construct SmallVector with iterator rang [...]
       new  329b887286a [Analysis, IR] Use *Map::lookup (NFC)
The 4 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
 .../SystemZ/builtins-systemz-zvector-constrained.c |    4 +-
 .../CodeGen/SystemZ/builtins-systemz-zvector.c     |   44 +-
 .../builtins-systemz-zvector2-constrained.c        |    8 +-
 .../CodeGen/SystemZ/builtins-systemz-zvector2.c    |    8 +-
 clang/test/CodeGen/SystemZ/zvector.c               |  128 +-
 clang/test/CodeGen/arm-mve-intrinsics/compare.c    |  336 ++---
 .../test/CodeGen/arm-mve-intrinsics/cplusplus.cpp  |    4 +-
 clang/test/CodeGen/arm-mve-intrinsics/dup.c        |   96 +-
 clang/test/CodeGen/arm-mve-intrinsics/ternary.c    |   80 +-
 clang/test/CodeGen/arm-mve-intrinsics/vaddq.c      |   24 +-
 clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c     |   36 +-
 clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c     |   36 +-
 clang/test/CodeGen/arm-mve-intrinsics/vmulq.c      |   48 +-
 clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c     |   24 +-
 clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c   |   24 +-
 clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c  |   16 +-
 clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c  |   16 +-
 clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c  |   24 +-
 clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c     |   24 +-
 clang/test/CodeGen/arm-mve-intrinsics/vsubq.c      |   24 +-
 clang/test/CodeGen/builtins-ppc-p10vector.c        |    8 +-
 clang/test/CodeGen/matrix-type-operators.c         |   60 +-
 clang/test/CodeGen/vecshift.c                      |   36 +-
 clang/test/CodeGenCXX/conditional-temporaries.cpp  |   25 +-
 clang/test/CodeGenCXX/matrix-type-operators.cpp    |   28 +-
 clang/test/CodeGenCXX/vector-conditional.cpp       |   76 +-
 clang/test/CodeGenCXX/vector-splat-conversion.cpp  |    4 +-
 clang/test/CodeGenOpenCL/bool_cast.cl              |    4 +-
 clang/test/CodeGenOpenCL/shifts.cl                 |    4 +-
 clang/test/Driver/aarch64-cpus.c                   |    8 +
 compiler-rt/lib/lsan/lsan_common.cpp               |  114 +-
 compiler-rt/lib/lsan/lsan_common_fuchsia.cpp       |    4 +-
 .../lib/sanitizer_common/sanitizer_common.h        |   32 +-
 .../lib/sanitizer_common/sanitizer_stackdepot.cpp  |    3 +-
 .../sanitizer_symbolizer_report.cpp                |    2 +-
 .../tests/sanitizer_common_test.cpp                |   69 +-
 compiler-rt/lib/tsan/dd/dd_interceptors.cpp        |   11 +-
 .../test/asan/TestCases/Linux/printf-fortify-1.c   |    2 +-
 .../test/asan/TestCases/Linux/printf-fortify-2.c   |    2 +-
 .../test/asan/TestCases/Linux/printf-fortify-3.c   |    2 +-
 .../test/asan/TestCases/Linux/printf-fortify-4.c   |    2 +-
 .../test/asan/TestCases/Linux/printf-fortify-5.c   |    2 +-
 .../TestCases/Linux/swapcontext_annotation.cpp     |    4 +-
 .../test/asan/TestCases/Linux/swapcontext_test.cpp |    4 +-
 .../test/asan/TestCases/malloc-no-intercept.c      |    2 +-
 .../test/lsan/TestCases/suppressions_file.cpp      |   16 +-
 compiler-rt/test/ubsan/TestCases/Misc/monitor.cpp  |    1 +
 lld/ELF/InputFiles.h                               |    7 +-
 lld/ELF/SyntheticSections.h                        |    7 +-
 lld/ELF/Writer.cpp                                 |    5 +-
 .../test/tools/lldb-server/gdbremote_testcase.py   |    4 +-
 lldb/source/Plugins/Process/POSIX/CrashReason.cpp  |   25 +
 lldb/source/Plugins/Process/POSIX/CrashReason.h    |    2 +
 .../API/tools/lldb-server/TestLldbGdbServer.py     |  226 +--
 llvm/include/llvm/Analysis/DDG.h                   |    2 +-
 llvm/include/llvm/Analysis/IntervalIterator.h      |    2 +-
 llvm/include/llvm/Analysis/RegionInfoImpl.h        |    9 +-
 llvm/include/llvm/Analysis/VectorUtils.h           |   10 +-
 llvm/include/llvm/CodeGen/CodeGenPassBuilder.h     | 1144 +++++++++++++++
 llvm/include/llvm/CodeGen/MachinePassRegistry.def  |  197 +++
 llvm/include/llvm/CodeGen/TargetPassConfig.h       |    4 +
 llvm/include/llvm/Demangle/ItaniumDemangle.h       |    8 +-
 llvm/include/llvm/Demangle/Utility.h               |    2 +-
 .../Orc/OrcRPCTargetProcessControl.h               |    4 +-
 .../ExecutionEngine/Orc/OrcRemoteTargetClient.h    |    9 +-
 .../ExecutionEngine/Orc/OrcRemoteTargetRPCAPI.h    |  282 ++--
 .../ExecutionEngine/Orc/OrcRemoteTargetServer.h    |    5 +-
 .../Orc/{RPC => Shared}/FDRawByteChannel.h         |   14 +-
 .../ExecutionEngine/Orc/{RPC => Shared}/RPCUtils.h |  250 ++--
 .../Orc/{RPC => Shared}/RawByteChannel.h           |   25 +-
 .../RPCSerialization.h => Shared/Serialization.h}  |  262 ++--
 .../Orc/TargetProcess/OrcRPCTPCServer.h            |   86 +-
 llvm/include/llvm/IR/IRBuilder.h                   |    4 +-
 llvm/include/llvm/IR/IntrinsicsRISCV.td            |   40 +-
 llvm/include/llvm/Support/AArch64TargetParser.def  |    3 +
 llvm/include/llvm/Support/ARMTargetParser.def      |    4 +-
 llvm/include/llvm/Target/CGPassBuilderOption.h     |   65 +
 llvm/include/llvm/Target/TargetMachine.h           |   29 +
 llvm/include/llvm/Transforms/IPO/IROutliner.h      |   41 +-
 .../llvm/Transforms/Scalar/InferAddressSpaces.h    |   27 +
 llvm/lib/Analysis/AliasSetTracker.cpp              |    2 +-
 llvm/lib/Analysis/CFGPrinter.cpp                   |    2 +-
 llvm/lib/Analysis/DDG.cpp                          |    2 +-
 llvm/lib/Analysis/DependenceGraphBuilder.cpp       |    3 +-
 llvm/lib/Analysis/IRSimilarityIdentifier.cpp       |   12 +-
 llvm/lib/Analysis/LazyValueInfo.cpp                |    2 +-
 llvm/lib/Analysis/MemorySSAUpdater.cpp             |    7 +-
 llvm/lib/Analysis/ScalarEvolution.cpp              |    4 +-
 llvm/lib/Analysis/TargetLibraryInfo.cpp            |    4 +-
 llvm/lib/CodeGen/AsmPrinter/WinCFGuard.cpp         |    3 +-
 llvm/lib/CodeGen/CMakeLists.txt                    |    1 +
 llvm/lib/CodeGen/CodeGenPassBuilder.cpp            |   25 +
 llvm/lib/CodeGen/CodeGenPrepare.cpp                |    2 +-
 llvm/lib/CodeGen/LLVMTargetMachine.cpp             |   35 +-
 llvm/lib/CodeGen/MachineFunction.cpp               |    2 +-
 llvm/lib/CodeGen/MachineModuleInfo.cpp             |    3 +-
 llvm/lib/CodeGen/MachineOutliner.cpp               |    6 +-
 llvm/lib/CodeGen/MachinePipeliner.cpp              |    2 +-
 llvm/lib/CodeGen/RDFLiveness.cpp                   |    4 +-
 llvm/lib/CodeGen/ReachingDefAnalysis.cpp           |    3 +-
 llvm/lib/CodeGen/RegAllocPBQP.cpp                  |    2 +-
 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp     |    4 +-
 .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp   |    2 +-
 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp |    2 +-
 .../CodeGen/SelectionDAG/StatepointLowering.cpp    |    2 +-
 llvm/lib/CodeGen/TargetPassConfig.cpp              |  161 ++-
 llvm/lib/ExecutionEngine/Orc/Shared/RPCError.cpp   |   14 +-
 llvm/lib/IR/IRBuilder.cpp                          |   11 +-
 llvm/lib/IR/PassRegistry.cpp                       |    6 +-
 llvm/lib/IR/SafepointIRVerifier.cpp                |    3 +-
 llvm/lib/Passes/PassBuilder.cpp                    |    3 +-
 llvm/lib/Passes/PassRegistry.def                   |    1 +
 llvm/lib/Target/AArch64/AArch64.td                 |   20 +
 llvm/lib/Target/AArch64/AArch64Subtarget.cpp       |    1 +
 llvm/lib/Target/AArch64/AArch64Subtarget.h         |    1 +
 llvm/lib/Target/AMDGPU/AMDGPU.h                    |    5 +
 .../Target/AMDGPU/AMDGPULowerKernelAttributes.cpp  |   37 +-
 llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp     |   26 +-
 llvm/lib/Target/ARM/ARM.td                         |   10 +
 llvm/lib/Target/ARM/ARMSubtarget.cpp               |    1 +
 llvm/lib/Target/ARM/ARMSubtarget.h                 |    1 +
 llvm/lib/Target/PowerPC/PPCISelLowering.cpp        |   10 +-
 llvm/lib/Target/PowerPC/PPCInstrVSX.td             |   14 +
 llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp |    4 +
 llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp      |    7 +-
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp        |   42 +-
 llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td    |  232 +++-
 llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td |   29 +
 llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h        |    3 +
 llvm/lib/Transforms/IPO/IROutliner.cpp             |  289 +++-
 .../Transforms/InstCombine/InstCombineAndOrXor.cpp |    8 +-
 llvm/lib/Transforms/Scalar/GVN.cpp                 |    2 +-
 llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp  |   94 +-
 llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp  |    8 +-
 llvm/lib/Transforms/Scalar/Reassociate.cpp         |    4 +-
 llvm/lib/Transforms/Scalar/SROA.cpp                |    4 +-
 llvm/lib/Transforms/Utils/Local.cpp                |    4 +-
 llvm/lib/Transforms/Utils/LoopUtils.cpp            |   35 +-
 llvm/lib/Transforms/Utils/LowerInvoke.cpp          |    2 +-
 .../Transforms/Utils/PromoteMemoryToRegister.cpp   |    2 +-
 .../Transforms/Utils/ScalarEvolutionExpander.cpp   |    6 +-
 llvm/lib/Transforms/Utils/SimplifyCFG.cpp          |  124 +-
 llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp    |  390 +++---
 .../test/CodeGen/AMDGPU/infer-addrpace-pipeline.ll |   15 +-
 llvm/test/CodeGen/AMDGPU/reqd-work-group-size.ll   |    1 +
 .../CodeGen/PowerPC/canonical-merge-shuffles.ll    |  149 +-
 llvm/test/CodeGen/PowerPC/load-and-splat.ll        |    3 +-
 llvm/test/CodeGen/PowerPC/peephole-cmp-eq.mir      |   44 +
 llvm/test/CodeGen/PowerPC/pr47916.ll               |   17 +
 llvm/test/CodeGen/PowerPC/pr48388.ll               |   41 +
 llvm/test/CodeGen/PowerPC/pr48519.ll               |   55 +
 llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll          |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll          |   88 +-
 llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll         |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll         |   88 +-
 llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll           |  108 +-
 llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll           |  132 +-
 llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll           |  108 +-
 llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll           |  132 +-
 llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll    | 1333 ++++++++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv64.ll    | 1305 +++++++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll          |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll          |   88 +-
 llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll         |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll         |   88 +-
 llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll      |  650 +++++++++
 llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll      |  830 +++++++++++
 llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll           |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll           |   88 +-
 llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll          |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll          |   88 +-
 llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll          |   44 +-
 llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll          |   60 +-
 llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll          |   44 +-
 llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll          |   60 +-
 llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll         |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll         |   96 +-
 llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll         |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll         |   96 +-
 llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll          |   44 +-
 llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll          |   60 +-
 llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll          |   44 +-
 llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll          |   60 +-
 llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll         |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll         |   96 +-
 llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll         |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll         |   96 +-
 llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll          |   44 +-
 llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll          |   60 +-
 llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll        |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll        |   96 +-
 llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll        |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll        |   96 +-
 llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll        |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll        |   96 +-
 llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll        |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll        |   96 +-
 llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll         |   22 +-
 llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll         |   30 +-
 llvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll         |   22 +-
 llvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll         |   30 +-
 llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll         |   44 +-
 llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll         |   60 +-
 llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll        |   44 +-
 llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll        |   60 +-
 llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll        |   44 +-
 llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll        |   60 +-
 llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll   |   22 +-
 llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll   |   30 +-
 llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll     |   22 +-
 llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll     |   30 +-
 llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll          |   44 +-
 llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll          |   60 +-
 llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll         |   20 +-
 llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll         |   36 +-
 llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll       |   20 +-
 llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll       |   36 +-
 llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll        |   40 +-
 llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll        |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll        |   40 +-
 llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll        |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll         |   20 +-
 llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll         |   36 +-
 llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll       |   40 +-
 llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll       |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll       |   40 +-
 llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll       |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll         |   20 +-
 llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll         |   36 +-
 llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll       |   20 +-
 llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll       |   36 +-
 llvm/test/CodeGen/RISCV/rvv/vid-rv32.ll            |   34 +-
 llvm/test/CodeGen/RISCV/rvv/vid-rv64.ll            |   42 +-
 llvm/test/CodeGen/RISCV/rvv/viota-rv32.ll          |   36 +-
 llvm/test/CodeGen/RISCV/rvv/viota-rv64.ll          |   44 +-
 llvm/test/CodeGen/RISCV/rvv/vle-rv32.ll            |   58 +-
 llvm/test/CodeGen/RISCV/rvv/vle-rv64.ll            |   74 +-
 llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll          |   58 +-
 llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll          |   74 +-
 llvm/test/CodeGen/RISCV/rvv/vlse-rv32.ll           |   58 +-
 llvm/test/CodeGen/RISCV/rvv/vlse-rv64.ll           |   74 +-
 llvm/test/CodeGen/RISCV/rvv/vlxe-rv32.ll           |  164 +--
 llvm/test/CodeGen/RISCV/rvv/vlxe-rv64.ll           |  268 ++--
 llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll          |  120 +-
 llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll          |  144 +-
 llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll          |  120 +-
 llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll          |  144 +-
 llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll           |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vmax-rv64.ll           |   88 +-
 llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll          |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vmaxu-rv64.ll          |   88 +-
 llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll          |   36 +-
 llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll          |   48 +-
 llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll          |   18 +-
 llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll          |   24 +-
 llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll          |   18 +-
 llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll          |   24 +-
 llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll          |   36 +-
 llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll          |   48 +-
 llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll          |   36 +-
 llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll          |   48 +-
 llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll          |   36 +-
 llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll          |   48 +-
 llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll           |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vmin-rv64.ll           |   88 +-
 llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll          |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vminu-rv64.ll          |   88 +-
 llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll          |  141 +-
 llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll          |  141 +-
 llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll          |   90 +-
 llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll          |  108 +-
 llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll          |   60 +-
 llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll          |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll         |   60 +-
 llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll         |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll          |  141 +-
 llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll          |  141 +-
 llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll          |   90 +-
 llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll          |  108 +-
 llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll         |   90 +-
 llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll         |  108 +-
 llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll          |   60 +-
 llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll          |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll         |   60 +-
 llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll         |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll          |   90 +-
 llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll          |  108 +-
 llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll          |  141 +-
 llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll          |  141 +-
 llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll           |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll           |   88 +-
 llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll          |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll          |   88 +-
 llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll        |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll        |   88 +-
 llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll         |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll         |   88 +-
 llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll         |   66 +-
 llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll         |   90 +-
 llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll        |   66 +-
 llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll        |   90 +-
 llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll         |  120 +-
 llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll         |  144 +-
 llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll         |  120 +-
 llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll         |  144 +-
 llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll          |   66 +-
 llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll          |   90 +-
 llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll          |   66 +-
 llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll          |   90 +-
 llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll            |  108 +-
 llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll            |  132 +-
 llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll           |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll           |   88 +-
 llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll          |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll          |   88 +-
 llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll       |  174 +--
 llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll       |  222 +--
 llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll          |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vrsub-rv64.ll          |   88 +-
 llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll   |  559 ++++++++
 llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv64.ll   |  531 +++++++
 llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll          |  108 +-
 llvm/test/CodeGen/RISCV/rvv/vsadd-rv64.ll          |  132 +-
 llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll         |  108 +-
 llvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll         |  132 +-
 llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll          |  664 +++++++++
 llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll          | 1162 ++++++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll    |   36 +-
 llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll    |   44 +-
 llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll      |   44 +-
 llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll     |  192 +--
 llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll     |  240 ++--
 llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll       |  192 +--
 llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll       |  240 ++--
 llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll           |  108 +-
 llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll           |  132 +-
 llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll          |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll          |   88 +-
 llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll           |  108 +-
 llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll           |  132 +-
 llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll    | 1069 ++++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv64.ll    | 1041 ++++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll           |  108 +-
 llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll           |  132 +-
 llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll          |  108 +-
 llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll          |  132 +-
 llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll          |  108 +-
 llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll          |  132 +-
 llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll          |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll          |   88 +-
 llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll         |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vssubu-rv64.ll         |   88 +-
 llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll           |   72 +-
 llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll           |   88 +-
 llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll    |  805 +++++++++++
 llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv64.ll    |  777 +++++++++++
 llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll          |   44 +-
 llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll          |   60 +-
 llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll        |   44 +-
 llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll        |   60 +-
 llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll         |   44 +-
 llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll         |   60 +-
 llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll       |   44 +-
 llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll       |   60 +-
 llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll         |   88 +-
 llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll         |  120 +-
 llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll       |   88 +-
 llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll       |  120 +-
 llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll        |   88 +-
 llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll        |  120 +-
 llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll       |   44 +-
 llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll       |   60 +-
 llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll          |   44 +-
 llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll          |   60 +-
 llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll        |   44 +-
 llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll        |   60 +-
 llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll         |   44 +-
 llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll         |   60 +-
 llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll          |   44 +-
 llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll          |   60 +-
 llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll        |   44 +-
 llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll        |   60 +-
 llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll         |   44 +-
 llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll         |   60 +-
 llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll       |   44 +-
 llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll       |   60 +-
 llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll           |  108 +-
 llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll           |  132 +-
 llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll    | 1333 ++++++++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv64.ll    | 1305 +++++++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll          |  664 +++++++++
 llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll          | 1162 ++++++++++++++++
 .../AArch64/gather-scatter-opt-inseltpoison.ll     |   12 +-
 .../AArch64/sink-free-instructions-inseltpoison.ll |  274 ++++
 .../ARM/sink-add-mul-shufflevector-inseltpoison.ll |   30 +-
 .../ARM/sink-free-instructions-inseltpoison.ll     |  232 ++++
 .../CodeGenPrepare/ARM/sinkchain-inseltpoison.ll   |   10 +-
 .../X86/cgp_shuffle_crash-inseltpoison.ll          |   14 +
 .../X86/gather-scatter-opt-inseltpoison.ll         |   12 +-
 .../CodeGenPrepare/X86/vec-shift-inseltpoison.ll   |  111 +-
 .../X86/x86-shuffle-sink-inseltpoison.ll           |   50 +-
 .../masked-dead-store-inseltpoison.ll              |   78 ++
 llvm/test/Transforms/GVN/preserve-memoryssa.ll     |   32 +
 llvm/test/Transforms/GVNSink/indirect-call.ll      |    2 +-
 llvm/test/Transforms/GVNSink/sink-common-code.ll   |    2 +-
 llvm/test/Transforms/IROutliner/extraction.ll      |    2 +-
 llvm/test/Transforms/IROutliner/illegal-allocas.ll |    2 +-
 llvm/test/Transforms/IROutliner/illegal-assumes.ll |    2 +-
 .../test/Transforms/IROutliner/illegal-branches.ll |    2 +-
 llvm/test/Transforms/IROutliner/illegal-callbr.ll  |    2 +-
 llvm/test/Transforms/IROutliner/illegal-calls.ll   |    2 +-
 .../test/Transforms/IROutliner/illegal-catchpad.ll |    2 +-
 llvm/test/Transforms/IROutliner/illegal-cleanup.ll |    2 +-
 llvm/test/Transforms/IROutliner/illegal-frozen.ll  |    2 +-
 llvm/test/Transforms/IROutliner/illegal-gep.ll     |    2 +-
 llvm/test/Transforms/IROutliner/illegal-invoke.ll  |    2 +-
 .../Transforms/IROutliner/illegal-landingpad.ll    |    2 +-
 llvm/test/Transforms/IROutliner/illegal-memcpy.ll  |    2 +-
 llvm/test/Transforms/IROutliner/illegal-memmove.ll |    2 +-
 llvm/test/Transforms/IROutliner/illegal-memset.ll  |    2 +-
 .../Transforms/IROutliner/illegal-phi-nodes.ll     |    2 +-
 llvm/test/Transforms/IROutliner/illegal-vaarg.ll   |    2 +-
 llvm/test/Transforms/IROutliner/legal-debug.ll     |    2 +-
 llvm/test/Transforms/IROutliner/opt-remarks.ll     |  184 +++
 .../IROutliner/outlining-address-taken.ll          |    2 +-
 .../IROutliner/outlining-commutative-fp.ll         |    2 +-
 .../Transforms/IROutliner/outlining-commutative.ll |    2 +-
 .../IROutliner/outlining-constants-vs-registers.ll |    2 +-
 .../Transforms/IROutliner/outlining-cost-model.ll  |  183 +++
 ...-constants.ll => outlining-debug-statements.ll} |   33 +-
 .../IROutliner/outlining-different-constants.ll    |    2 +-
 .../IROutliner/outlining-different-globals.ll      |    2 +-
 .../outlining-different-output-blocks.ll           |    2 +-
 .../IROutliner/outlining-different-structure.ll    |    2 +-
 .../IROutliner/outlining-remapped-outputs.ll       |    2 +-
 .../IROutliner/outlining-same-constants.ll         |    2 +-
 .../IROutliner/outlining-same-globals.ll           |    2 +-
 .../IROutliner/outlining-same-output-blocks.ll     |    2 +-
 .../AMDGPU/infer-address-space.ll                  |    1 +
 .../Inline/inlined-loop-metadata-inseltpoison.ll   |  159 +++
 .../amdgcn-demanded-vector-elts-inseltpoison.ll    |  250 ++--
 .../X86/shufflemask-undef-inseltpoison.ll          |  110 ++
 .../InstCombine/X86/x86-addsub-inseltpoison.ll     |   38 +-
 .../InstCombine/X86/x86-avx2-inseltpoison.ll       |  110 ++
 .../InstCombine/X86/x86-f16c-inseltpoison.ll       |   71 +
 .../InstCombine/X86/x86-muldq-inseltpoison.ll      |  281 ++++
 .../InstCombine/X86/x86-pack-inseltpoison.ll       |   60 +-
 .../InstCombine/X86/x86-pshufb-inseltpoison.ll     |  515 +++++++
 .../InstCombine/X86/x86-sse4a-inseltpoison.ll      |  420 ++++++
 .../X86/x86-vector-shifts-inseltpoison.ll          |  106 +-
 .../InstCombine/X86/x86-vector-shifts.ll           |   36 +-
 .../InstCombine/X86/x86-vpermil-inseltpoison.ll    |  301 ++++
 .../Transforms/InstCombine/assume-inseltpoison.ll  |  656 +++++++++
 .../Transforms/InstCombine/bswap-inseltpoison.ll   |  867 ++++++++++++
 .../InstCombine/extractelement-inseltpoison.ll     |    2 +-
 .../Transforms/InstCombine/fmul-inseltpoison.ll    | 1176 ++++++++++++++++
 .../Transforms/InstCombine/gep-inbounds-null.ll    |    2 +-
 llvm/test/Transforms/InstCombine/getelementptr.ll  |    4 +-
 .../hoist-xor-by-constant-from-xor-by-value.ll     |   20 +
 .../InstCombine/icmp-bc-vec-inseltpoison.ll        |   22 +-
 .../InstCombine/icmp-vec-inseltpoison.ll           |  375 +++++
 .../insert-extract-shuffle-inseltpoison.ll         |   62 +-
 .../InstCombine/logical-select-inseltpoison.ll     |  637 +++++++++
 .../InstCombine/masked_intrinsics-inseltpoison.ll  |    4 +-
 .../Transforms/InstCombine/mul-inseltpoison.ll     | 1108 +++++++++++++++
 .../Transforms/InstCombine/nsw-inseltpoison.ll     |  142 ++
 .../InstCombine/obfuscated_splat-inseltpoison.ll   |   11 +
 .../InstCombine/pr2645-0-inseltpoison.ll           |   34 +
 .../InstCombine/scalarization-inseltpoison.ll      |    2 +-
 .../select-extractelement-inseltpoison.ll          |    4 +-
 .../InstCombine/shift-add-inseltpoison.ll          |   12 +-
 .../InstCombine/shuffle-cast-inseltpoison.ll       |  123 ++
 ...ow.ll => shuffle-select-narrow-inseltpoison.ll} |   68 +-
 .../InstCombine/shuffle-select-narrow.ll           |   12 +-
 .../InstCombine/shuffle_select-inseltpoison.ll     | 1467 ++++++++++++++++++++
 .../InstCombine/shufflevec-bitcast-inseltpoison.ll |  169 +++
 .../shufflevec-constant-inseltpoison.ll            |   17 +
 .../shufflevector-div-rem-inseltpoison.ll          |   22 +-
 .../InstCombine/sub-of-negatible-inseltpoison.ll   | 1406 +++++++++++++++++++
 .../trunc-extractelement-inseltpoison.ll           |    4 +-
 .../Transforms/InstCombine/trunc-inseltpoison.ll   | 1023 ++++++++++++++
 .../{type_pun.ll => type_pun-inseltpoison.ll}      |   22 +-
 llvm/test/Transforms/InstCombine/type_pun.ll       |    2 +-
 .../InstCombine/vec-binop-select-inseltpoison.ll   |  287 ++++
 .../InstCombine/vec_demanded_elts-inseltpoison.ll  |  160 +--
 .../InstCombine/vec_gep_scalar_arg-inseltpoison.ll |    2 +-
 .../InstCombine/vec_phi_extract-inseltpoison.ll    |    6 +-
 .../InstCombine/vec_shuffle-inseltpoison.ll        |  430 +++---
 llvm/test/Transforms/InstCombine/vec_shuffle.ll    |   16 +-
 .../vector-concat-binop-inseltpoison.ll            |  282 ++++
 .../InstCombine/vector_gep1-inseltpoison.ll        |    4 +-
 llvm/test/Transforms/InstCombine/vscale_cmp.ll     |    8 +-
 .../vscale_extractelement-inseltpoison.ll          |   16 +-
 .../vscale_insertelement-inseltpoison.ll           |    4 +-
 .../ConstProp/vector-undef-elts-inseltpoison.ll    |   69 +
 .../InstSimplify/ConstProp/vscale-inseltpoison.ll  |    8 +-
 .../InstSimplify/shufflevector-inseltpoison.ll     |  286 ++++
 .../Transforms/InstSimplify/vscale-inseltpoison.ll |    8 +-
 .../AArch64/binopshuffles-inseltpoison.ll          |  151 ++
 ...terleaved-accesses-extract-user-inseltpoison.ll |  113 ++
 .../AArch64/interleaved-accesses-inseltpoison.ll   |  801 +++++++++++
 ...terleaved-accesses-extract-user-inseltpoison.ll |  113 ++
 .../ARM/interleaved-accesses-inseltpoison.ll       | 1432 +++++++++++++++++++
 ...interleaved-accesses-64bits-avx-inseltpoison.ll |  243 ++++
 .../X86/interleavedLoad-inseltpoison.ll            |  158 +++
 .../X86/interleavedStore-inseltpoison.ll           |  243 ++++
 .../LoopSimplify/do-preheader-dbg-inseltpoison.ll  |  122 ++
 .../AMDGPU/lsr-void-inseltpoison.ll                |   37 +
 .../ARM/vctp-chains-inseltpoison.ll                |   16 +-
 .../p8-unrolling-legalize-vectors-inseltpoison.ll  |    4 +-
 .../LoopUnroll/X86/pr46430-inseltpoison.ll         |   23 +
 .../AArch64/arbitrary-induction-step.ll            |   12 +-
 .../outer_loop_test1_no_explicit_vect_width.ll     |    8 +-
 .../ARM/mve-gather-scatter-tailpred.ll             |   20 +-
 .../LoopVectorize/ARM/mve-reduction-types.ll       |   36 +-
 .../Transforms/LoopVectorize/ARM/pointer_iv.ll     |   82 +-
 .../LoopVectorize/ARM/tail-folding-not-allowed.ll  |    2 +-
 .../PowerPC/optimal-epilog-vectorization.ll        |  680 +++++++--
 .../LoopVectorize/X86/consecutive-ptr-uniforms.ll  |    8 +-
 .../Transforms/LoopVectorize/X86/constant-fold.ll  |   10 +-
 .../LoopVectorize/X86/cost-model-assert.ll         |   16 +-
 .../Transforms/LoopVectorize/X86/interleaving.ll   |    4 +-
 .../LoopVectorize/X86/invariant-load-gather.ll     |   16 +-
 .../X86/invariant-store-vectorization.ll           |   48 +-
 .../LoopVectorize/X86/load-deref-pred.ll           |   16 +-
 .../LoopVectorize/X86/masked_load_store.ll         |   64 +-
 .../LoopVectorize/X86/metadata-enable.ll           |   84 +-
 llvm/test/Transforms/LoopVectorize/X86/optsize.ll  |  162 ++-
 .../X86/outer_loop_test1_no_explicit_vect_width.ll |    8 +-
 llvm/test/Transforms/LoopVectorize/X86/pr34438.ll  |    4 +-
 .../Transforms/LoopVectorize/X86/small-size.ll     |   24 +-
 .../LoopVectorize/X86/tail_loop_folding.ll         |   16 +-
 .../Transforms/LoopVectorize/X86/uniform_mem_op.ll |   48 +-
 .../LoopVectorize/X86/vect.omp.force.small-tc.ll   |   20 +-
 .../X86/x86-interleaved-accesses-masked-group.ll   |  174 +--
 .../LoopVectorize/consecutive-ptr-uniforms.ll      |    4 +-
 .../LoopVectorize/dont-fold-tail-for-const-TC.ll   |    4 +-
 .../dont-fold-tail-for-divisible-TC.ll             |    4 +-
 .../first-order-recurrence-complex.ll              |    8 +-
 .../Transforms/LoopVectorize/float-induction.ll    |   44 +-
 .../LoopVectorize/float-minmax-instruction-flag.ll |    8 +-
 .../Transforms/LoopVectorize/if-pred-stores.ll     |    8 +-
 .../Transforms/LoopVectorize/induction-step.ll     |   32 +-
 llvm/test/Transforms/LoopVectorize/induction.ll    |   12 +-
 .../LoopVectorize/interleaved-accesses-1.ll        |    4 +-
 .../interleaved-accesses-pred-stores.ll            |    6 +-
 .../LoopVectorize/interleaved-accesses.ll          |   58 +-
 .../LoopVectorize/invariant-store-vectorization.ll |   14 +-
 llvm/test/Transforms/LoopVectorize/loop-form.ll    |    4 +-
 .../Transforms/LoopVectorize/minmax_reduction.ll   |    4 +-
 .../multiple-strides-vectorization.ll              |    4 +-
 .../LoopVectorize/optimal-epilog-vectorization.ll  |  119 +-
 llvm/test/Transforms/LoopVectorize/optsize.ll      |    4 +-
 .../Transforms/LoopVectorize/outer_loop_test1.ll   |    4 +-
 .../Transforms/LoopVectorize/outer_loop_test2.ll   |    8 +-
 .../Transforms/LoopVectorize/pointer-induction.ll  |   66 +-
 .../LoopVectorize/pr39417-optsize-scevchecks.ll    |    4 +-
 .../LoopVectorize/pr44488-predication.ll           |    8 +-
 .../LoopVectorize/pr46525-expander-insertpoint.ll  |   52 +-
 .../scalable-loop-unpredicated-body-scalar-tail.ll |    6 +-
 .../Transforms/LoopVectorize/select-reduction.ll   |   12 +-
 llvm/test/Transforms/LoopVectorize/vector-geps.ll  |    4 +-
 .../bigger-expressions-double.ll                   |  895 ++++++------
 .../Transforms/LowerMatrixIntrinsics/const-gep.ll  |   32 +-
 .../multiply-add-sub-double-row-major.ll           |   48 +-
 .../multiply-double-contraction-fmf.ll             |   32 +-
 .../multiply-double-contraction.ll                 |   32 +-
 .../multiply-double-row-major.ll                   |  123 +-
 .../LowerMatrixIntrinsics/multiply-double.ll       |  120 +-
 .../multiply-float-contraction-fmf.ll              |   32 +-
 .../multiply-float-contraction.ll                  |   32 +-
 .../LowerMatrixIntrinsics/multiply-float.ll        |  120 +-
 .../LowerMatrixIntrinsics/multiply-fused-loops.ll  |  224 +--
 .../multiply-fused-multiple-blocks.ll              |  420 +++---
 .../multiply-fused-volatile.ll                     |  408 +++---
 .../LowerMatrixIntrinsics/multiply-fused.ll        |   32 +-
 .../multiply-i32-row-major.ll                      |  123 +-
 .../LowerMatrixIntrinsics/multiply-i32.ll          |  120 +-
 .../X86/scalarization-inseltpoison.ll              |   18 +-
 .../Transforms/PhaseOrdering/X86/scalarization.ll  |    2 +-
 .../X86/{shuffle.ll => shuffle-inseltpoison.ll}    |  100 +-
 llvm/test/Transforms/PhaseOrdering/X86/shuffle.ll  |   14 +-
 llvm/test/Transforms/PhaseOrdering/X86/vdiv.ll     |    4 +-
 .../PhaseOrdering/X86/vector-reductions.ll         |   14 +-
 .../RewriteStatepointsForGC/scalar-base-vector.ll  |   12 +-
 .../Transforms/SLPVectorizer/AArch64/PR38339.ll    |    6 +-
 llvm/test/Transforms/SLPVectorizer/X86/PR32086.ll  |    6 +-
 llvm/test/Transforms/SLPVectorizer/X86/PR39774.ll  |    4 +-
 llvm/test/Transforms/SLPVectorizer/X86/PR40310.ll  |    2 +-
 .../Transforms/SLPVectorizer/X86/commutativity.ll  |   38 +-
 .../X86/external_user_jumbled_load-inseltpoison.ll |    2 +-
 .../X86/external_user_jumbled_load.ll              |   12 +-
 llvm/test/Transforms/SLPVectorizer/X86/extract.ll  |   10 +-
 llvm/test/Transforms/SLPVectorizer/X86/hoist.ll    |    2 +-
 .../insert-element-build-vector-inseltpoison.ll    |    6 +-
 .../X86/insert-element-build-vector.ll             |   12 +-
 .../SLPVectorizer/X86/jumbled-load-multiuse.ll     |    6 +-
 .../X86/jumbled-load-shuffle-placement.ll          |    8 +-
 .../SLPVectorizer/X86/jumbled-load-used-in-phi.ll  |    8 +-
 .../Transforms/SLPVectorizer/X86/jumbled-load.ll   |   18 +-
 .../SLPVectorizer/X86/jumbled_store_crash.ll       |    6 +-
 .../SLPVectorizer/X86/load-merge-inseltpoison.ll   |    2 +-
 .../Transforms/SLPVectorizer/X86/load-merge.ll     |    2 +-
 llvm/test/Transforms/SLPVectorizer/X86/partail.ll  |    2 +-
 llvm/test/Transforms/SLPVectorizer/X86/phi.ll      |   12 +-
 llvm/test/Transforms/SLPVectorizer/X86/pr47623.ll  |    2 +-
 .../SLPVectorizer/X86/reduction_loads.ll           |    4 +-
 .../SLPVectorizer/X86/reorder_repeated_ops.ll      |    4 +-
 .../X86/reuse-extracts-in-wider-vect.ll            |    2 +-
 .../Transforms/SLPVectorizer/X86/store-jumbled.ll  |    2 +-
 .../SLPVectorizer/X86/stores_vectorize.ll          |    2 +-
 .../SLPVectorizer/X86/vectorize-reorder-reuse.ll   |    6 +-
 .../Transforms/SLPVectorizer/slp-max-phi-size.ll   |    4 +-
 .../Transforms/Scalarizer/basic-inseltpoison.ll    |    2 +-
 .../Scalarizer/dbgloc-bug-inseltpoison.ll          |    2 +-
 .../Scalarizer/order-bug-inseltpoison.ll           |    2 +-
 .../Transforms/Scalarizer/phi-bug-inseltpoison.ll  |   25 +
 llvm/test/Transforms/Scalarizer/vector-gep.ll      |   12 +-
 .../SimplifyCFG/2004-12-10-SimplifyCFGCrash.ll     |    2 +-
 .../Transforms/SimplifyCFG/2005-06-16-PHICrash.ll  |    2 +-
 .../SimplifyCFG/2008-07-13-InfLoopMiscompile.ll    |    2 +-
 llvm/test/Transforms/SimplifyCFG/BrUnwind.ll       |    2 +-
 llvm/test/Transforms/SimplifyCFG/HoistCode.ll      |    2 +-
 llvm/test/Transforms/SimplifyCFG/InfLoop.ll        |    2 +-
 .../Transforms/SimplifyCFG/UncondBranchToReturn.ll |    2 +-
 .../Transforms/SimplifyCFG/X86/critedge-assume.ll  |    2 +-
 .../Transforms/SimplifyCFG/X86/empty-cleanuppad.ll |    2 +-
 llvm/test/Transforms/SimplifyCFG/X86/pr39187-g.ll  |    2 +-
 .../Transforms/SimplifyCFG/branch-phi-thread.ll    |    2 +-
 .../SimplifyCFG/debug-info-thread-phi.ll           |    2 +-
 llvm/test/Transforms/SimplifyCFG/extract-cost.ll   |    2 +-
 .../Transforms/SimplifyCFG/hoist-common-code.ll    |    2 +-
 .../Transforms/SimplifyCFG/hoist-with-range.ll     |    2 +-
 .../SimplifyCFG/implied-cond-matching-imm.ll       |    2 +-
 .../Transforms/SimplifyCFG/iterative-simplify.ll   |    2 +-
 .../Transforms/SimplifyCFG/merge-cond-stores-2.ll  |    2 +-
 .../Transforms/SimplifyCFG/merge-cond-stores.ll    |    2 +-
 llvm/test/Transforms/SimplifyCFG/pr34131.ll        |    2 +-
 llvm/test/Transforms/SimplifyCFG/pr39807.ll        |    2 +-
 llvm/test/Transforms/SimplifyCFG/pr46638.ll        |    2 +-
 .../SimplifyCFG/preserve-store-alignment.ll        |    2 +-
 .../Transforms/SimplifyCFG/sink-common-code.ll     |    2 +-
 .../SimplifyCFG/switch-on-const-select.ll          |    2 +-
 .../test/Transforms/SimplifyCFG/unprofitable-pr.ll |    2 +-
 .../spec-other-inseltpoison.ll                     |    2 +-
 .../AArch64/vscale-bitcast-shuffle-inseltpoison.ll |   21 +
 .../AMDGPU/as-transition-inseltpoison.ll           |    2 +-
 .../VectorCombine/AMDGPU/as-transition.ll          |    2 +-
 .../X86/extract-binop-inseltpoison.ll              |   40 +-
 .../Transforms/VectorCombine/X86/extract-binop.ll  |   40 +-
 .../VectorCombine/X86/extract-cmp-binop.ll         |    8 +-
 .../Transforms/VectorCombine/X86/extract-cmp.ll    |   10 +-
 .../VectorCombine/X86/load-inseltpoison.ll         |   38 +-
 llvm/test/Transforms/VectorCombine/X86/load.ll     |   38 +-
 .../VectorCombine/X86/no-sse-inseltpoison.ll       |   15 +
 .../X86/{shuffle.ll => shuffle-inseltpoison.ll}    |   50 +-
 llvm/test/Transforms/VectorCombine/X86/shuffle.ll  |   50 +-
 llvm/tools/lli/ChildTarget/ChildTarget.cpp         |    6 +-
 llvm/tools/lli/RemoteJITUtils.h                    |    4 +-
 llvm/tools/lli/lli.cpp                             |    8 +-
 .../llvm-jitlink-executor.cpp                      |    8 +-
 llvm/tools/llvm-jitlink/llvm-jitlink.cpp           |   10 +-
 llvm/tools/llvm-jitlink/llvm-jitlink.h             |    8 +-
 llvm/tools/opt/opt.cpp                             |    3 +-
 llvm/unittests/ExecutionEngine/Orc/QueueChannel.h  |   12 +-
 .../unittests/ExecutionEngine/Orc/RPCUtilsTest.cpp |  104 +-
 llvm/unittests/Support/TargetParserTest.cpp        |   19 +-
 llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn  |    1 +
 mlir/include/mlir/Bindings/Python/Attributes.td    |   16 +-
 mlir/include/mlir/IR/OpBase.td                     |   11 +-
 mlir/lib/Bindings/Python/IRModules.cpp             |   44 +-
 .../Dialect/Linalg/Transforms/Vectorization.cpp    |   83 +-
 mlir/lib/Dialect/Vector/VectorOps.cpp              |   18 +-
 mlir/lib/Pass/PassRegistry.cpp                     |   11 +-
 mlir/lib/Transforms/Inliner.cpp                    |    4 +
 mlir/test/Bindings/Python/ir_attributes.py         |   14 +
 mlir/test/Bindings/Python/ir_operation.py          |   27 +-
 mlir/test/Dialect/Linalg/vectorization.mlir        |  107 +-
 mlir/test/Pass/invalid-pass.mlir                   |    6 +
 mlir/test/mlir-tblgen/op-python-bindings.td        |  148 +-
 mlir/test/mlir-tblgen/rewriter-indexing.td         |    8 +
 mlir/test/mlir-tblgen/types.mlir                   |    2 +-
 mlir/tools/mlir-tblgen/OpPythonBindingGen.cpp      |   61 +-
 mlir/tools/mlir-tblgen/RewriterGen.cpp             |    2 +-
 .../Isl/CodeGen/invariant_load_hoist_alignment.ll  |    2 +-
 polly/test/Isl/CodeGen/simple_vec_cast.ll          |    4 +-
 polly/test/Isl/CodeGen/simple_vec_const.ll         |    4 +-
 polly/test/Isl/CodeGen/simple_vec_ptr_ptr_ty.ll    |    4 +-
 688 files changed, 49877 insertions(+), 14121 deletions(-)
 create mode 100644 llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
 create mode 100644 llvm/include/llvm/CodeGen/MachinePassRegistry.def
 rename llvm/include/llvm/ExecutionEngine/Orc/{RPC => Shared}/FDRawByteChannel.h (87%)
 rename llvm/include/llvm/ExecutionEngine/Orc/{RPC => Shared}/RPCUtils.h (89%)
 rename llvm/include/llvm/ExecutionEngine/Orc/{RPC => Shared}/RawByteChannel.h (88%)
 rename llvm/include/llvm/ExecutionEngine/Orc/{RPC/RPCSerialization.h => Shared/Ser [...]
 create mode 100644 llvm/include/llvm/Target/CGPassBuilderOption.h
 create mode 100644 llvm/include/llvm/Transforms/Scalar/InferAddressSpaces.h
 create mode 100644 llvm/lib/CodeGen/CodeGenPassBuilder.cpp
 create mode 100644 llvm/test/CodeGen/PowerPC/peephole-cmp-eq.mir
 create mode 100644 llvm/test/CodeGen/PowerPC/pr47916.ll
 create mode 100644 llvm/test/CodeGen/PowerPC/pr48388.ll
 create mode 100644 llvm/test/CodeGen/PowerPC/pr48519.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll
 create mode 100644 llvm/test/Transforms/CodeGenPrepare/AArch64/sink-free-instructi [...]
 create mode 100644 llvm/test/Transforms/CodeGenPrepare/ARM/sink-free-instructions- [...]
 create mode 100644 llvm/test/Transforms/CodeGenPrepare/X86/cgp_shuffle_crash-insel [...]
 create mode 100644 llvm/test/Transforms/DeadStoreElimination/masked-dead-store-ins [...]
 create mode 100644 llvm/test/Transforms/IROutliner/opt-remarks.ll
 create mode 100644 llvm/test/Transforms/IROutliner/outlining-cost-model.ll
 copy llvm/test/Transforms/IROutliner/{outlining-same-constants.ll => outlining-deb [...]
 create mode 100755 llvm/test/Transforms/Inline/inlined-loop-metadata-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/X86/shufflemask-undef-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-avx2-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-f16c-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-muldq-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-pshufb-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-sse4a-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/X86/x86-vpermil-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/assume-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/bswap-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/fmul-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/icmp-vec-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/mul-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/nsw-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/obfuscated_splat-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/pr2645-0-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/shuffle-cast-inseltpoison.ll
 copy llvm/test/Transforms/InstCombine/{shuffle-select-narrow.ll => shuffle-select- [...]
 create mode 100644 llvm/test/Transforms/InstCombine/shuffle_select-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/shufflevec-bitcast-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/shufflevec-constant-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/sub-of-negatible-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll
 copy llvm/test/Transforms/InstCombine/{type_pun.ll => type_pun-inseltpoison.ll} (82%)
 create mode 100644 llvm/test/Transforms/InstCombine/vec-binop-select-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstCombine/vector-concat-binop-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InstSimplify/ConstProp/vector-undef-elts-i [...]
 create mode 100644 llvm/test/Transforms/InstSimplify/shufflevector-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/InterleavedAccess/AArch64/binopshuffles-in [...]
 create mode 100644 llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-acce [...]
 create mode 100644 llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-acce [...]
 create mode 100644 llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses [...]
 create mode 100644 llvm/test/Transforms/InterleavedAccess/ARM/interleaved-accesses [...]
 create mode 100644 llvm/test/Transforms/InterleavedAccess/X86/interleaved-accesses [...]
 create mode 100644 llvm/test/Transforms/InterleavedAccess/X86/interleavedLoad-inse [...]
 create mode 100644 llvm/test/Transforms/InterleavedAccess/X86/interleavedStore-ins [...]
 create mode 100755 llvm/test/Transforms/LoopSimplify/do-preheader-dbg-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-void-inseltp [...]
 create mode 100644 llvm/test/Transforms/LoopUnroll/X86/pr46430-inseltpoison.ll
 copy llvm/test/Transforms/PhaseOrdering/X86/{shuffle.ll => shuffle-inseltpoison.ll} (71%)
 create mode 100644 llvm/test/Transforms/Scalarizer/phi-bug-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/VectorCombine/AArch64/vscale-bitcast-shuff [...]
 create mode 100644 llvm/test/Transforms/VectorCombine/X86/no-sse-inseltpoison.ll
 copy llvm/test/Transforms/VectorCombine/X86/{shuffle.ll => shuffle-inseltpoison.ll} (74%)
 create mode 100644 mlir/test/Pass/invalid-pass.mlir
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[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allyesconfig updated (1e23802507d -> 329b887286a)