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from ee326d639ba [Hexagon] Add patterns for any_extend from i1 and short vec [...] new e6fa3d9af74 [Hexagon] Check if operand is an immediate before getImm new e7dca1ec056 [GlobalISel] Restrict G_MERGE_VALUES capability and replace [...]
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Summary of changes: .../GlobalISel/LegalizationArtifactCombiner.h | 16 +- include/llvm/CodeGen/GlobalISel/LegalizerInfo.h | 14 + lib/CodeGen/GlobalISel/IRTranslator.cpp | 10 +- lib/CodeGen/GlobalISel/Legalizer.cpp | 2 + lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 41 ++- lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 4 + lib/CodeGen/MachineVerifier.cpp | 26 ++ lib/Target/AArch64/AArch64InstructionSelector.cpp | 128 +++++++++ lib/Target/AArch64/AArch64LegalizerInfo.cpp | 14 +- lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 8 + lib/Target/Hexagon/HexagonOptAddrMode.cpp | 27 +- lib/Target/X86/X86InstructionSelector.cpp | 4 +- lib/Target/X86/X86LegalizerInfo.cpp | 14 +- .../AArch64/GlobalISel/arm64-irtranslator.ll | 28 +- test/CodeGen/AArch64/GlobalISel/legalize-add.mir | 9 +- .../AArch64/GlobalISel/legalize-build-vector.mir | 41 +++ .../GlobalISel/legalize-extract-vector-elt.mir | 21 ++ .../GlobalISel/legalize-nonpowerof2eltsvec.mir | 33 --- .../AArch64/GlobalISel/legalizer-combiner.mir | 25 ++ .../GlobalISel/legalizer-info-validation.mir | 2 +- .../AArch64/GlobalISel/select-build-vector.mir | 301 +++++++++++++++++++++ .../GlobalISel/legalize-extract-vector-elt.mir | 20 +- ....mir => legalize-merge-values-build-vector.mir} | 18 +- .../AMDGPU/GlobalISel/legalize-unmerge-values.mir | 15 - test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll | 12 +- test/CodeGen/Hexagon/addrmode-immop.mir | 40 +++ .../X86/GlobalISel/irtranslator-callingconv.ll | 16 +- test/CodeGen/X86/GlobalISel/legalize-add-v256.mir | 16 +- test/CodeGen/X86/GlobalISel/legalize-add-v512.mir | 24 +- .../CodeGen/X86/GlobalISel/select-merge-vec256.mir | 2 +- .../CodeGen/X86/GlobalISel/select-merge-vec512.mir | 4 +- 31 files changed, 775 insertions(+), 160 deletions(-) create mode 100644 test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir create mode 100644 test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir delete mode 100644 test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir create mode 100644 test/CodeGen/AArch64/GlobalISel/legalizer-combiner.mir create mode 100644 test/CodeGen/AArch64/GlobalISel/select-build-vector.mir rename test/CodeGen/AMDGPU/GlobalISel/{legalize-merge-values.mir => legalize-merge [...] create mode 100644 test/CodeGen/Hexagon/addrmode-immop.mir