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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allnoconfig in repository toolchain/ci/llvm-project.
from 486d1a53589 Revert "[clang][modules] Add support for merging lifetime-e [...] adds 89c47313c9b remove UB from test by making GV alignment explicit adds 35bc5276ca3 [libunwind] Emit dependent libraries only when detected by CMake adds 3dd93dc2a1a [X86][InstCombine] Move instcombine test from test/CodeGen/ [...] adds 67298d683ca [X86][InstCombine] Move non-X86 specific instcombine test f [...] adds a3cbe1a202d [clang][modules] Add support for merging lifetime-extended [...] adds ae5484540f1 Revert "[clang][modules] Add support for merging lifetime-e [...] adds 19fd8925a4a Revert "[Examples] Add IRTransformations directory to examples." adds 259ca0418ee [SCEV] Make SCEV verification available from command line w [...] adds cfbbdc83b41 AMDGPU/GlobalISel: Add AGPR bank and RegBankSelect mfma intrinsics adds 269c1c703d5 Fix broken comment phrasing and indentation adds 497a754adec [Clang-Tidy] Quick fix for bug in bugprone-macro-parentheses 43804 adds bd23859f390 [NFC] Precommit test showing SROA loses `!tbaa.struct` metadata adds c653a52c85f [llvm-readobj/llvm-readelf] - Reimplement dumping of the SH [...] adds 902dc6c69ce [clangd] Fix a regression issue in local rename. adds 5c05b4a279f [Orc] Add setters for target options and features to JITTar [...] adds 0e7ecc651a4 [ExecutionEngine] Add a jitTargetAddressToFunction utility [...] adds ece8fed6090 [ORC] Add a runAsMain utility function to ExecutionUtils. adds 7eecf2b872e [llvm-readelf/llvm-readobj] - Check the version of SHT_GNU_ [...] adds a9d6b0e5444 [InstCombine] Fix big-endian miscompile of (bitcast (zext/t [...] adds 44b9942898c [X86] Add initialization of MXCSR in llvm-exegesis adds e9e1daf2b9e [ARM] Remove VHADD patterns adds 160a5045c69 [lldb][NFC] Add 'breakpoint command list' test adds d9542db49e9 [UpdateTestChecks] Share the code to parse RUN: lines betwe [...] adds 8ab3b4defd9 [update_cc_test_checks.py] Handle extern "C" and namespaces adds 510792a2e0e [ARM][MVE][Intrinsics] Add VMINQ/VMAXQ/VMINNMQ/VMAXNMQ intrinsics. adds f8fb3729e9d [lldb][NFC] Make Stream's IndentLevel an unsigned integers. adds 3d5ba7c60f3 AMDGPU: Fixed indeterminate map iteration in SIPeepholeSDWA adds e19f19b09f8 [llvm-readobj/llvm-readelf] - Simplify the code that dumps [...] adds 76b70f6f75e [X86] Add initialization of FPCW in llvm-exegesis new 4f728bfc13c [lldb][NFC] Use raw_ostream instead of Stream in Baton::Get [...]
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Summary of changes: .../clang-tidy/bugprone/MacroParenthesesCheck.cpp | 2 +- clang-tools-extra/clangd/refactor/Rename.cpp | 18 +- clang-tools-extra/clangd/unittests/RenameTests.cpp | 9 +- .../checkers/bugprone-macro-parentheses.cpp | 1 + clang/include/clang/Basic/arm_mve.td | 42 + clang/include/clang/Basic/arm_mve_defs.td | 1 + clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c | 65 ++ clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c | 98 +++ clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c | 65 ++ clang/test/CodeGen/arm-mve-intrinsics/vminq.c | 98 +++ libunwind/CMakeLists.txt | 7 +- libunwind/src/AddressSpace.hpp | 2 +- libunwind/src/RWMutex.hpp | 2 +- lldb/include/lldb/Breakpoint/BreakpointOptions.h | 3 +- lldb/include/lldb/Breakpoint/WatchpointOptions.h | 3 +- lldb/include/lldb/Utility/Baton.h | 13 +- lldb/include/lldb/Utility/Stream.h | 12 +- .../command/list/TestBreakpointCommandList.py | 44 + .../test/commands/breakpoint/command/list/a.yaml | 18 + lldb/source/Breakpoint/BreakpointOptions.cpp | 37 +- lldb/source/Breakpoint/WatchpointOptions.cpp | 28 +- .../Commands/CommandObjectBreakpointCommand.cpp | 8 +- .../Commands/CommandObjectWatchpointCommand.cpp | 8 +- lldb/source/Target/Target.cpp | 2 +- lldb/source/Utility/Baton.cpp | 5 +- lldb/source/Utility/Stream.cpp | 10 +- llvm/CMakeLists.txt | 4 - llvm/examples/CMakeLists.txt | 1 - llvm/examples/IRTransforms/CMakeLists.txt | 15 - llvm/examples/IRTransforms/InitializePasses.cpp | 21 - llvm/examples/IRTransforms/InitializePasses.h | 22 - llvm/examples/IRTransforms/SimplifyCFG.cpp | 414 --------- llvm/examples/IRTransforms/SimplifyCFG.h | 24 - llvm/examples/SpeculativeJIT/SpeculativeJIT.cpp | 15 +- llvm/include/llvm/Analysis/ScalarEvolution.h | 7 + llvm/include/llvm/ExecutionEngine/JITSymbol.h | 18 + .../llvm/ExecutionEngine/Orc/ExecutionUtils.h | 11 + .../ExecutionEngine/Orc/JITTargetMachineBuilder.h | 17 + llvm/include/llvm/IR/IntrinsicsARM.td | 6 + llvm/lib/Analysis/ScalarEvolution.cpp | 6 + llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp | 26 + .../Orc/JITTargetMachineBuilder.cpp | 4 +- llvm/lib/Passes/PassRegistry.def | 1 + .../Target/AMDGPU/AMDGPUGenRegisterBankInfo.def | 64 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 69 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h | 6 + llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td | 4 + llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp | 5 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 13 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 5 + llvm/lib/Target/ARM/ARMInstrMVE.td | 147 ++-- .../Transforms/InstCombine/InstCombineCasts.cpp | 79 +- .../GlobalISel/regbankselect-amdgcn.mfma.mir | 943 +++++++++++++++++++++ llvm/test/CodeGen/Thumb2/mve-intrinsics/vmaxnmq.ll | 61 ++ llvm/test/CodeGen/Thumb2/mve-intrinsics/vmaxq.ll | 89 ++ llvm/test/CodeGen/Thumb2/mve-intrinsics/vminnmq.ll | 62 ++ llvm/test/CodeGen/Thumb2/mve-intrinsics/vminq.ll | 89 ++ llvm/test/CodeGen/Thumb2/mve-vhaddsub.ll | 72 +- .../SimplifyCFG/tut-simplify-cfg-blockaddress.ll | 23 - .../IRTransforms/SimplifyCFG/tut-simplify-cfg1.ll | 90 -- .../tut-simplify-cfg2-dead-block-order.ll | 109 --- .../SimplifyCFG/tut-simplify-cfg3-phis.ll | 70 -- ...simplify-cfg4-multiple-duplicate-cfg-updates.ll | 40 - .../tut-simplify-cfg5-del-phis-for-dead-block.ll | 122 --- .../tut-simplify-cfg6-dead-self-loop.ll | 25 - llvm/test/Transforms/GlobalOpt/atomic.ll | 8 +- .../InstCombine}/X86/2009-03-23-i80-fp80.ll | 10 +- llvm/test/Transforms/InstCombine/cast.ll | 33 +- .../InstCombine}/vec_udiv_to_shift.ll | 0 llvm/test/Transforms/SROA/tbaa-struct.ll | 32 + llvm/test/tools/llvm-exegesis/X86/uops-ADD_F32m.s | 9 + .../tools/llvm-exegesis/X86/uops-VFMADDSS4rm.s | 3 + .../tools/llvm-readobj/elf-verdef-invalid.test | 45 + .../tools/llvm-readobj/elf-verneed-invalid.test | 357 +++++++- llvm/tools/lli/lli.cpp | 15 +- llvm/tools/llvm-exegesis/lib/X86/Target.cpp | 23 + llvm/tools/llvm-jitlink/llvm-jitlink.cpp | 23 +- llvm/tools/llvm-readobj/ELFDumper.cpp | 434 +++++----- llvm/tools/opt/CMakeLists.txt | 4 - llvm/tools/opt/opt.cpp | 8 - llvm/utils/UpdateTestChecks/common.py | 31 +- llvm/utils/update_analyze_test_checks.py | 28 +- llvm/utils/update_cc_test_checks.py | 63 +- llvm/utils/update_llc_test_checks.py | 40 +- llvm/utils/update_mca_test_checks.py | 30 +- llvm/utils/update_mir_test_checks.py | 19 +- llvm/utils/update_test_checks.py | 28 +- 87 files changed, 2952 insertions(+), 1691 deletions(-) create mode 100644 clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c create mode 100644 clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c create mode 100644 clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c create mode 100644 clang/test/CodeGen/arm-mve-intrinsics/vminq.c create mode 100644 lldb/packages/Python/lldbsuite/test/commands/breakpoint/command [...] create mode 100644 lldb/packages/Python/lldbsuite/test/commands/breakpoint/command [...] delete mode 100644 llvm/examples/IRTransforms/CMakeLists.txt delete mode 100644 llvm/examples/IRTransforms/InitializePasses.cpp delete mode 100644 llvm/examples/IRTransforms/InitializePasses.h delete mode 100644 llvm/examples/IRTransforms/SimplifyCFG.cpp delete mode 100644 llvm/examples/IRTransforms/SimplifyCFG.h create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir create mode 100644 llvm/test/CodeGen/Thumb2/mve-intrinsics/vmaxnmq.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-intrinsics/vmaxq.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-intrinsics/vminnmq.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-intrinsics/vminq.ll delete mode 100644 llvm/test/Examples/IRTransforms/SimplifyCFG/tut-simplify-cfg-bl [...] delete mode 100644 llvm/test/Examples/IRTransforms/SimplifyCFG/tut-simplify-cfg1.ll delete mode 100644 llvm/test/Examples/IRTransforms/SimplifyCFG/tut-simplify-cfg2-d [...] delete mode 100644 llvm/test/Examples/IRTransforms/SimplifyCFG/tut-simplify-cfg3-phis.ll delete mode 100644 llvm/test/Examples/IRTransforms/SimplifyCFG/tut-simplify-cfg4-m [...] delete mode 100644 llvm/test/Examples/IRTransforms/SimplifyCFG/tut-simplify-cfg5-d [...] delete mode 100644 llvm/test/Examples/IRTransforms/SimplifyCFG/tut-simplify-cfg6-d [...] rename llvm/test/{CodeGen => Transforms/InstCombine}/X86/2009-03-23-i80-fp80.ll (58%) rename llvm/test/{CodeGen/X86 => Transforms/InstCombine}/vec_udiv_to_shift.ll (100%) create mode 100644 llvm/test/Transforms/SROA/tbaa-struct.ll create mode 100644 llvm/test/tools/llvm-exegesis/X86/uops-ADD_F32m.s