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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allyesconfig in repository toolchain/ci/llvm-project.
from 0f21545a3c9 [sanitizer] Calculate SizeClassAllocator32::ByteMap type fr [...] adds b907c442653 [lldb] [lit] Cleanly terminate Register tests adds b82144b6e4b [cmake] Disable a GCC optimization when building LLVM for MIPS adds d77dc9ada20 [MCA] Add field `IsEliminated` to class Instruction. NFCI adds acc1e6d1c61 [X86][AVX] Merge mask select with shuffles across extract_s [...] adds 3879b2cd45e [X86][SSE] Add initial test case for subvector insert/extra [...] adds 0969af6962e [llvm-nm] Support section type 'u': STB_GNU_UNIQUE adds 795c00b21f0 [DJB] Fix variable case after D61178 adds 5cf616530a1 Fix check-prefixes typo adds 763a2e1f360 [llvm-nm][llvm-readelf] Avoid single-dash -long-option in tests adds 15c072a1619 [lli] Fix a typo in a cl::opt description. adds 913bfd3363f [X86] Add vector boolean reduction tests (PR38840) adds 2a2d4224002 [X86][AVX512] Improve vector bool reductions adds e2849a031c0 Fix UNPREDICTABLE check in EmulateInstructionARM::EmulateAD [...] adds 399746eaf6f [X86][AVX] Cleanup and add additional expandload and compre [...] adds 4118be3af60 [X86][SSE] Add support for <64 x i1> bool reduction adds 1a4a43250ed [X86][AVX] Add additional SSE/AVX expandload and compressst [...] adds 03c4e2663ce Revert rL359389: [X86][SSE] Add support for <64 x i1> bool [...] adds bd35a309403 [X86] Remove (V)MOV64toSDrr/m and (V)MOVDI2SSrr/m. Use 128- [...] adds 8eeb33497cd [PowerPC][Clang] Add tests for PowerPC MMX intrinsics
No new revisions were added by this update.
Summary of changes: clang/test/CodeGen/ppc-mmintrin.c | 1284 ++++- lldb/lit/Register/x86-64-read.test | 3 + lldb/lit/Register/x86-64-ymm-read.test | 3 + lldb/lit/Register/x86-mm-xmm-read.test | 3 + lldb/lit/Register/x86-ymm-read.test | 3 + .../Instruction/ARM/EmulateInstructionARM.cpp | 2 +- llvm/cmake/modules/HandleLLVMOptions.cmake | 5 + llvm/include/llvm/MCA/Instruction.h | 14 +- llvm/lib/MCA/Stages/DispatchStage.cpp | 6 +- llvm/lib/Support/DJB.cpp | 6 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 81 +- llvm/lib/Target/X86/X86InstrAVX512.td | 29 +- llvm/lib/Target/X86/X86InstrFoldTables.cpp | 6 - llvm/lib/Target/X86/X86InstrSSE.td | 57 +- .../CodeGen/X86/avx512-shuffles/partial_permute.ll | 239 +- llvm/test/CodeGen/X86/evex-to-vex-compress.mir | 16 - llvm/test/CodeGen/X86/fast-isel-fneg.ll | 13 +- llvm/test/CodeGen/X86/masked_compressstore.ll | 5325 ++++++++++++++++---- llvm/test/CodeGen/X86/masked_expandload.ll | 5091 +++++++++++++++---- llvm/test/CodeGen/X86/oddsubvector.ll | 84 + llvm/test/CodeGen/X86/peephole.mir | 40 - llvm/test/CodeGen/X86/pr41619.ll | 27 + llvm/test/CodeGen/X86/vector-compare-all_of.ll | 175 +- llvm/test/CodeGen/X86/vector-compare-any_of.ll | 188 +- llvm/test/CodeGen/X86/vector-reduce-and-bool.ll | 1461 ++++++ llvm/test/CodeGen/X86/vector-reduce-or-bool.ll | 1455 ++++++ llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll | 2556 ++++++++++ .../DebugInfo/X86/xray-split-dwarf-interaction.ll | 2 +- llvm/test/DebugInfo/debuglineinfo-path.ll | 6 +- llvm/test/LTO/X86/runtime-library.ll | 2 +- llvm/test/MC/Mips/tls-symbols.s | 5 +- llvm/test/Other/llvm-nm-without-aliases.ll | 6 +- llvm/test/ThinLTO/X86/cache-icall.ll | 4 +- llvm/test/tools/gold/X86/bcsection.ll | 4 +- llvm/test/tools/llvm-ar/coff-weak.yaml | 2 +- llvm/test/tools/llvm-nm/X86/IRobj.test | 2 +- llvm/test/tools/llvm-nm/X86/dyldinfo.test | 4 +- llvm/test/tools/llvm-nm/X86/radix.s | 10 +- .../elf-reloc-symbol-with-versioning.test | 4 +- llvm/test/tools/llvm-readobj/elf-versioninfo.test | 4 +- llvm/test/tools/lto/opt-level.ll | 4 +- llvm/test/tools/yaml2obj/dynamic-symbols.yaml | 2 +- llvm/test/tools/yaml2obj/symbol-index.yaml | 2 +- llvm/tools/lli/lli.cpp | 2 +- 44 files changed, 15753 insertions(+), 2484 deletions(-) create mode 100644 llvm/test/CodeGen/X86/oddsubvector.ll delete mode 100644 llvm/test/CodeGen/X86/peephole.mir create mode 100644 llvm/test/CodeGen/X86/pr41619.ll create mode 100644 llvm/test/CodeGen/X86/vector-reduce-and-bool.ll create mode 100644 llvm/test/CodeGen/X86/vector-reduce-or-bool.ll create mode 100644 llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll