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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-defconfig in repository toolchain/ci/llvm-project.
from 4e972224c47 AMDGPU/GlobalISel: Refine SMRD selection rules adds 1f950ced504 GlobalISel: Define G_READCYCLECOUNTER adds 99f74a64a2d [SCEV] Remove unused ScalarEvolutionExpander.h includes (NFC). adds 51ef53f3bd2 [SCEV] Move ScalarEvolutionExpander.cpp to Transforms/Utils (NFC). adds b8a3c34eee0 Revert "[SCEV] Move ScalarEvolutionExpander.cpp to Transfor [...] adds d12f2a29984 GlobalISel: Scalarize all division operations adds 085898d469a [ELF] Drop const qualifier to fix -Wrange-loop-analysis. NFC adds 285d5e6b8b1 [LegalizeVectorOps] Split most of ExpandStrictFPOp into a s [...] adds 16a67d252c7 [TargetLowering] In expandFP_TO_UINT, add proper extend or [...] adds 4e37d60f2a6 [LegalizeVectorOps][X86] Enable expansion of vector fp_to_u [...] adds 170de3de2ee [ParserTest] Move raw string literal out of macro adds 5a253992212 [ARM] Add and update FMA tests. NFC adds c15a56f61a5 [ARM] Fill in FP16 FMA patterns adds fb8c9a339a9 [ARM] Use isFMAFasterThanFMulAndFAdd for scalars as well as [...] adds 3db84f142af [X86] Merge (identical) LowerGC_TRANSITION_START and LowerG [...] new 6a6e6f04ec2 [X86] Move combineLogicBlendIntoConditionalNegate before co [...]
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Summary of changes: clang/unittests/ASTMatchers/Dynamic/ParserTest.cpp | 6 +- lld/ELF/Relocations.cpp | 2 +- llvm/include/llvm/Support/TargetOpcodes.def | 3 + llvm/include/llvm/Target/GenericOpcodes.td | 6 + .../llvm/Target/GlobalISel/SelectionDAGCompat.td | 1 + llvm/lib/Analysis/IVDescriptors.cpp | 1 - llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 2 + llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 3 + .../lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 25 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 4 + llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 7 + llvm/lib/Target/ARM/ARM.td | 17 + llvm/lib/Target/ARM/ARMISelLowering.cpp | 11 +- llvm/lib/Target/ARM/ARMInstrVFP.td | 21 + llvm/lib/Target/ARM/ARMPredicates.td | 8 +- llvm/lib/Target/ARM/ARMSubtarget.h | 9 + llvm/lib/Target/ARM/ARMTargetTransformInfo.h | 18 +- llvm/lib/Target/PowerPC/PPCCTRLoops.cpp | 1 - llvm/lib/Target/X86/X86ISelLowering.cpp | 152 +++---- llvm/lib/Target/X86/X86ISelLowering.h | 3 +- llvm/lib/Transforms/Utils/LoopUnrollAndJam.cpp | 1 - llvm/lib/Transforms/Utils/LoopUtils.cpp | 1 - .../AArch64/GlobalISel/arm64-irtranslator.ll | 10 + .../GlobalISel/legalizer-info-validation.mir | 5 + .../CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir | 451 ++++++++++++++++++++ .../CodeGen/AMDGPU/GlobalISel/legalize-srem.mir | 457 +++++++++++++++++++++ .../CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir | 412 +++++++++++++++++++ .../CodeGen/AMDGPU/GlobalISel/legalize-urem.mir | 412 +++++++++++++++++++ llvm/test/CodeGen/ARM/cortex-a57-misched-vfma.ll | 18 +- llvm/test/CodeGen/ARM/fp16-fullfp16.ll | 2 +- llvm/test/CodeGen/ARM/fp16-fusedMAC.ll | 429 +++++++++++++++++++ llvm/test/CodeGen/ARM/fusedMAC.ll | 50 +-- .../test/CodeGen/Thumb2/float-intrinsics-double.ll | 2 +- llvm/test/CodeGen/Thumb2/float-intrinsics-float.ll | 2 +- llvm/test/CodeGen/X86/vec-strict-fptoint-128.ll | 156 ++----- llvm/test/CodeGen/X86/vec-strict-fptoint-256.ll | 148 ++----- .../X86/vector-constrained-fp-intrinsics.ll | 61 +-- 37 files changed, 2501 insertions(+), 416 deletions(-) create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir create mode 100644 llvm/test/CodeGen/ARM/fp16-fusedMAC.ll