[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-O3 updated (47251582f5c -> 466590192b4)

31 Aug 2020


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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-O3
in repository toolchain/ci/llvm-project.
from  47251582f5c [SimplifyCFG] Cost required selects
      adds  33bb80bc7a6 [X86] ia32intrin.h - pull out common attributes into define [...]
      adds  18bc400f97a [NewPM][PassInstrumentation] Add PreservedAnalyses paramete [...]
      adds  90e0a021291 [Attributor][NFC] run update_test_checks with --check-attributes.
      adds  98de0d22f57 [AMDGPU] Apply llvm-prefer-register-over-unsigned from clang-tidy
      adds  f7e4e87df34 [DSE,MemorySSA] Regenerate check lines for atomic.ll tests.
      adds  c6863a4ab8b [X86] Enable constexpr on POPCNT intrinsics (PR31446)
      adds  0819a6416fd [SelectionDAG] Better legalization for FSHL and FSHR
      adds  5d7c5a5e997 [NFC] Port InstCount pass to new pass manager
      adds  9f7350672e3 [DSE,MemorySSA] Handle atomicrmw/cmpxchg conservatively.
      adds  c8e6bf0a65f [X86] Enable constexpr on BSWAP intrinsics (PR31446)
      adds  c66b82f14cc [llvm-readelf] - Start recognizing 'PT_OPENBSD_*' segment types.
      adds  5bd1febe214 [AMDGPU] Fix alignment requirements for 96bit and 128bit lo [...]
      adds  f5cd7ec9f3f [AMDGPU] Reorganize GCN subtarget features for unaligned access
      adds  d17ea67b92f [AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores
      adds  0654ff703d4 [AMDGPU] Use ds_read/write_b96/b128 when possible for SDag
      adds  9e6c09c0d99 [RISCV] Fix inaccurate annotations on PseudoBRIND
      adds  9ffc412e1af [X86] Enable constexpr on BITSCAN intrinsics (PR31446)
      adds  1dd85e9d0e0 [NFC] Add SimplifyCFG for ARM
      adds  f5643dc3dce Recommit: [DWARFYAML] Add support for referencing different [...]
      adds  b4889353207 [clangd] Discard diagnostics from another SourceManager.
      adds  3f7985e6ec2 [AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax des [...]
      adds  519b0e3e9d6 [PowerPC] Pre-commit FISel with PC-Rel test
      adds  aa456a6df49 [llvm-readobj/elf] - Refine the code for broken PT_DYNAMIC  [...]
      adds  57903cf0933 [compiler-rt][RISCV] Use muldi3 builtin assembly implementation
      adds  88dd7c85497 [llvm-readelf][test] - Refine the merged.test
      adds  bfc6d8b59b7 [NFC][SimplifyCFG] Formatting and variable rename
      adds  88818491b9d [LoopIdiom,LSR] Add additional tests for SCEVExpander cleanups.
      adds  a4c3ed42ba5 Correctly emit dwoIDs after ASTFileSignature refactoring (D81347)
      adds  466590192b4 [AST][RecoveryExpr] Fix a bogus unused diagnostic when the  [...]
No new revisions were added by this update.
Summary of changes:
 clang-tools-extra/clangd/Diagnostics.cpp           |   16 +-
 clang-tools-extra/clangd/Diagnostics.h             |    4 +-
 .../clangd/unittests/ModulesTests.cpp              |   28 +
 clang/docs/ReleaseNotes.rst                        |   14 +-
 clang/include/clang/Basic/Module.h                 |    9 +
 clang/lib/AST/Expr.cpp                             |    2 +
 clang/lib/CodeGen/CGDebugInfo.cpp                  |    9 +-
 .../CodeGen/ObjectFilePCHContainerOperations.cpp   |    6 +-
 clang/lib/Headers/ia32intrin.h                     |   70 +-
 clang/test/CodeGen/bitscan-builtins.c              |   41 +-
 clang/test/CodeGen/popcnt-builtins.c               |   14 +
 clang/test/CodeGen/x86-bswap.c                     |   26 +-
 clang/test/Modules/Inputs/DebugDwoId.h             |    4 +
 clang/test/Modules/Inputs/module.map               |    4 +
 clang/test/Modules/ModuleDebugInfoDwoId.cpp        |   20 +
 clang/test/SemaCXX/recovery-expr-type.cpp          |   11 +
 compiler-rt/lib/builtins/CMakeLists.txt            |    5 +-
 llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst                | 1569 +++++-----
 llvm/docs/AMDGPU/AMDGPUAsmGFX1011.rst              |    6 +-
 llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst                 |  272 +-
 llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst                 |  926 +++---
 llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst                 | 1065 ++++---
 llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst               |    6 +-
 llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst               |    6 +-
 .../{gfx10_src32_3.rst => gfx1011_src32_2.rst}     |    4 +-
 .../{gfx10_src32_2.rst => gfx1011_src32_3.rst}     |    4 +-
 llvm/docs/AMDGPU/gfx10_addr_mimg.rst               |    2 +-
 llvm/docs/AMDGPU/gfx10_attr.rst                    |    1 -
 llvm/docs/AMDGPU/gfx10_bimm16.rst                  |    1 -
 llvm/docs/AMDGPU/gfx10_bimm32.rst                  |    1 -
 llvm/docs/AMDGPU/gfx10_data_smem_atomic64.rst      |    2 +-
 llvm/docs/AMDGPU/gfx10_fimm16.rst                  |    1 -
 llvm/docs/AMDGPU/gfx10_fimm32.rst                  |    1 -
 llvm/docs/AMDGPU/gfx10_hwreg.rst                   |    1 -
 llvm/docs/AMDGPU/gfx10_label.rst                   |    1 -
 llvm/docs/AMDGPU/gfx10_mad_type_dev.rst            |    1 -
 llvm/docs/AMDGPU/gfx10_mod_dpp_sdwa_abs_neg.rst    |    1 -
 llvm/docs/AMDGPU/gfx10_mod_sdwa_sext.rst           |    1 -
 llvm/docs/AMDGPU/gfx10_mod_vop3_abs_neg.rst        |    1 -
 llvm/docs/AMDGPU/gfx10_opt.rst                     |    1 -
 llvm/docs/AMDGPU/gfx10_param.rst                   |    1 -
 llvm/docs/AMDGPU/gfx10_perm_smem.rst               |    1 -
 llvm/docs/AMDGPU/gfx10_ret.rst                     |    1 -
 llvm/docs/AMDGPU/gfx10_sdata64_0.rst               |    2 +-
 llvm/docs/AMDGPU/gfx10_sdst64_0.rst                |    2 +-
 llvm/docs/AMDGPU/gfx10_sdst64_1.rst                |    2 +-
 llvm/docs/AMDGPU/gfx10_simm16.rst                  |    1 -
 llvm/docs/AMDGPU/gfx10_src32_1.rst                 |    2 +-
 llvm/docs/AMDGPU/gfx10_src32_2.rst                 |    2 +-
 llvm/docs/AMDGPU/gfx10_src32_3.rst                 |    2 +-
 .../{gfx10_src32_2.rst => gfx10_src32_4.rst}       |    2 +-
 .../{gfx10_src32_2.rst => gfx10_src32_5.rst}       |    4 +-
 .../{gfx10_src32_3.rst => gfx10_src32_6.rst}       |    2 +-
 llvm/docs/AMDGPU/gfx10_ssrc64_0.rst                |    2 +-
 llvm/docs/AMDGPU/gfx10_ssrc64_1.rst                |    2 +-
 llvm/docs/AMDGPU/gfx10_tgt.rst                     |    1 -
 llvm/docs/AMDGPU/gfx10_type_dev.rst                |    1 -
 llvm/docs/AMDGPU/gfx10_uimm16.rst                  |    1 -
 llvm/docs/AMDGPU/gfx10_vaddr_flat_global.rst       |    2 -
 llvm/docs/AMDGPU/gfx10_vcc_32.rst                  |    1 -
 llvm/docs/AMDGPU/gfx10_waitcnt.rst                 |    1 -
 llvm/docs/AMDGPU/gfx7_attr.rst                     |    1 -
 llvm/docs/AMDGPU/gfx7_bimm16.rst                   |    1 -
 llvm/docs/AMDGPU/gfx7_bimm32.rst                   |    1 -
 .../{gfx10_sdata64_0.rst => gfx7_dst_buf_32.rst}   |   10 +-
 llvm/docs/AMDGPU/gfx7_fimm32.rst                   |    1 -
 llvm/docs/AMDGPU/gfx7_hwreg.rst                    |    1 -
 llvm/docs/AMDGPU/gfx7_label.rst                    |    1 -
 llvm/docs/AMDGPU/gfx7_mod.rst                      |    1 -
 llvm/docs/AMDGPU/gfx7_opt.rst                      |    1 -
 llvm/docs/AMDGPU/gfx7_param.rst                    |    1 -
 llvm/docs/AMDGPU/gfx7_ret.rst                      |    1 -
 llvm/docs/AMDGPU/gfx7_simm16.rst                   |    1 -
 llvm/docs/AMDGPU/gfx7_tgt.rst                      |    1 -
 llvm/docs/AMDGPU/gfx7_type_dev.rst                 |    1 -
 llvm/docs/AMDGPU/gfx7_uimm16.rst                   |    1 -
 llvm/docs/AMDGPU/gfx7_waitcnt.rst                  |    1 -
 llvm/docs/AMDGPU/gfx8_attr.rst                     |    1 -
 llvm/docs/AMDGPU/gfx8_bimm16.rst                   |    1 -
 llvm/docs/AMDGPU/gfx8_bimm32.rst                   |    1 -
 .../{gfx10_sdata64_0.rst => gfx8_dst_buf_32.rst}   |   10 +-
 llvm/docs/AMDGPU/gfx8_fimm16.rst                   |    1 -
 llvm/docs/AMDGPU/gfx8_fimm32.rst                   |    1 -
 llvm/docs/AMDGPU/gfx8_hwreg.rst                    |    1 -
 llvm/docs/AMDGPU/gfx8_imask.rst                    |    1 -
 llvm/docs/AMDGPU/gfx8_label.rst                    |    1 -
 llvm/docs/AMDGPU/gfx8_mod_dpp_sdwa_abs_neg.rst     |    1 -
 llvm/docs/AMDGPU/gfx8_mod_sdwa_sext.rst            |    1 -
 llvm/docs/AMDGPU/gfx8_mod_vop3_abs_neg.rst         |    1 -
 llvm/docs/AMDGPU/gfx8_opt.rst                      |    1 -
 llvm/docs/AMDGPU/gfx8_param.rst                    |    1 -
 llvm/docs/AMDGPU/gfx8_perm_smem.rst                |    1 -
 llvm/docs/AMDGPU/gfx8_ret.rst                      |    1 -
 llvm/docs/AMDGPU/gfx8_simm16.rst                   |    1 -
 llvm/docs/AMDGPU/gfx8_src32_1.rst                  |    2 +-
 llvm/docs/AMDGPU/gfx8_src32_2.rst                  |    2 +-
 llvm/docs/AMDGPU/gfx8_src32_3.rst                  |    2 +-
 .../AMDGPU/{gfx8_src32_2.rst => gfx8_src32_4.rst}  |    2 +-
 .../AMDGPU/{gfx8_src32_3.rst => gfx8_src32_5.rst}  |    2 +-
 .../AMDGPU/{gfx8_src32_2.rst => gfx8_src32_6.rst}  |    4 +-
 .../AMDGPU/{gfx8_src32_3.rst => gfx8_src32_7.rst}  |    4 +-
 llvm/docs/AMDGPU/gfx8_tgt.rst                      |    1 -
 llvm/docs/AMDGPU/gfx8_type_dev.rst                 |    1 -
 llvm/docs/AMDGPU/gfx8_uimm16.rst                   |    1 -
 llvm/docs/AMDGPU/gfx8_waitcnt.rst                  |    1 -
 llvm/docs/AMDGPU/gfx900_mad_type_dev.rst           |    1 -
 llvm/docs/AMDGPU/gfx900_mod_vop3_abs_neg.rst       |    1 -
 llvm/docs/AMDGPU/gfx900_src32_0.rst                |    2 +-
 llvm/docs/AMDGPU/gfx900_src32_1.rst                |    2 +-
 llvm/docs/AMDGPU/gfx904_mad_type_dev.rst           |    1 -
 llvm/docs/AMDGPU/gfx904_mod_vop3_abs_neg.rst       |    1 -
 llvm/docs/AMDGPU/gfx904_src32_0.rst                |    2 +-
 llvm/docs/AMDGPU/gfx904_src32_1.rst                |    2 +-
 llvm/docs/AMDGPU/gfx906_mad_type_dev.rst           |    1 -
 llvm/docs/AMDGPU/gfx906_mod_dpp_sdwa_abs_neg.rst   |    1 -
 llvm/docs/AMDGPU/gfx906_mod_sdwa_sext.rst          |    1 -
 llvm/docs/AMDGPU/gfx906_mod_vop3_abs_neg.rst       |    1 -
 llvm/docs/AMDGPU/gfx906_src32_0.rst                |    2 +-
 llvm/docs/AMDGPU/gfx906_src32_1.rst                |    2 +-
 llvm/docs/AMDGPU/gfx906_src32_2.rst                |    2 +-
 .../{gfx9_src32_2.rst => gfx906_src32_3.rst}       |    4 +-
 .../{gfx9_src32_3.rst => gfx906_src32_4.rst}       |    4 +-
 llvm/docs/AMDGPU/gfx906_type_dev.rst               |    1 -
 llvm/docs/AMDGPU/gfx908_mad_type_dev.rst           |    1 -
 llvm/docs/AMDGPU/gfx908_mod_dpp_sdwa_abs_neg.rst   |    1 -
 llvm/docs/AMDGPU/gfx908_mod_sdwa_sext.rst          |    1 -
 llvm/docs/AMDGPU/gfx908_mod_vop3_abs_neg.rst       |    1 -
 llvm/docs/AMDGPU/gfx908_offset_buf.rst             |    2 +-
 llvm/docs/AMDGPU/gfx908_opt.rst                    |    1 -
 llvm/docs/AMDGPU/gfx908_ret.rst                    |    1 -
 llvm/docs/AMDGPU/gfx908_saddr_flat_global.rst      |    2 +-
 llvm/docs/AMDGPU/gfx908_src32_0.rst                |    2 +-
 llvm/docs/AMDGPU/gfx908_src32_1.rst                |    2 +-
 llvm/docs/AMDGPU/gfx908_src32_2.rst                |    2 +-
 llvm/docs/AMDGPU/gfx908_src32_3.rst                |    2 +-
 .../{gfx9_src32_2.rst => gfx908_src32_4.rst}       |    4 +-
 .../{gfx9_src32_3.rst => gfx908_src32_5.rst}       |    4 +-
 llvm/docs/AMDGPU/gfx908_type_dev.rst               |    1 -
 llvm/docs/AMDGPU/gfx908_vaddr_flat_global.rst      |    2 -
 llvm/docs/AMDGPU/gfx9_attr.rst                     |    1 -
 llvm/docs/AMDGPU/gfx9_bimm16.rst                   |    1 -
 llvm/docs/AMDGPU/gfx9_bimm32.rst                   |    1 -
 llvm/docs/AMDGPU/gfx9_fimm16.rst                   |    1 -
 llvm/docs/AMDGPU/gfx9_fimm32.rst                   |    1 -
 llvm/docs/AMDGPU/gfx9_hwreg.rst                    |    1 -
 llvm/docs/AMDGPU/gfx9_imask.rst                    |    1 -
 llvm/docs/AMDGPU/gfx9_label.rst                    |    1 -
 llvm/docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.rst     |    1 -
 llvm/docs/AMDGPU/gfx9_mod_sdwa_sext.rst            |    1 -
 llvm/docs/AMDGPU/gfx9_mod_vop3_abs_neg.rst         |    1 -
 llvm/docs/AMDGPU/gfx9_opt.rst                      |    1 -
 llvm/docs/AMDGPU/gfx9_param.rst                    |    1 -
 llvm/docs/AMDGPU/gfx9_perm_smem.rst                |    1 -
 llvm/docs/AMDGPU/gfx9_ret.rst                      |    1 -
 llvm/docs/AMDGPU/gfx9_simm16.rst                   |    1 -
 llvm/docs/AMDGPU/gfx9_src32_1.rst                  |    2 +-
 llvm/docs/AMDGPU/gfx9_src32_2.rst                  |    2 +-
 llvm/docs/AMDGPU/gfx9_src32_3.rst                  |    2 +-
 .../AMDGPU/{gfx9_src32_2.rst => gfx9_src32_4.rst}  |    2 +-
 .../AMDGPU/{gfx9_src32_3.rst => gfx9_src32_5.rst}  |    2 +-
 .../AMDGPU/{gfx9_src32_2.rst => gfx9_src32_6.rst}  |    4 +-
 .../AMDGPU/{gfx9_src32_3.rst => gfx9_src32_7.rst}  |    4 +-
 llvm/docs/AMDGPU/gfx9_tgt.rst                      |    1 -
 llvm/docs/AMDGPU/gfx9_type_dev.rst                 |    1 -
 llvm/docs/AMDGPU/gfx9_uimm16.rst                   |    1 -
 llvm/docs/AMDGPU/gfx9_vaddr_flat_global.rst        |    2 -
 llvm/docs/AMDGPU/gfx9_waitcnt.rst                  |    1 -
 llvm/docs/AMDGPUInstructionNotation.rst            |    2 +-
 llvm/docs/AMDGPUInstructionSyntax.rst              |    6 +-
 llvm/docs/AMDGPUModifierSyntax.rst                 |  211 +-
 llvm/docs/AMDGPUOperandSyntax.rst                  |   17 +-
 llvm/include/llvm/Analysis/CGSCCPassManager.h      |   10 +-
 llvm/include/llvm/Analysis/InstCount.h             |   28 +
 llvm/include/llvm/IR/PassInstrumentation.h         |   14 +-
 llvm/include/llvm/IR/PassManager.h                 |    9 +-
 llvm/include/llvm/InitializePasses.h               |    2 +-
 llvm/include/llvm/ObjectYAML/DWARFYAML.h           |    7 +
 .../llvm/Transforms/Scalar/LoopPassManager.h       |    6 +-
 llvm/lib/Analysis/Analysis.cpp                     |    2 +-
 llvm/lib/Analysis/CGSCCPassManager.cpp             |    4 +-
 llvm/lib/Analysis/InstCount.cpp                    |   87 +-
 llvm/lib/CodeGen/MachinePassManager.cpp            |    2 +-
 .../CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp  |   73 +
 llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h      |    5 +
 .../CodeGen/SelectionDAG/LegalizeVectorTypes.cpp   |    8 +
 .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp   |   58 +-
 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp   |   12 +
 llvm/lib/IR/PassTimingInfo.cpp                     |    8 +-
 llvm/lib/ObjectYAML/DWARFEmitter.cpp               |   26 +-
 llvm/lib/ObjectYAML/DWARFYAML.cpp                  |   29 +
 llvm/lib/Passes/PassBuilder.cpp                    |    1 +
 llvm/lib/Passes/PassRegistry.def                   |    1 +
 llvm/lib/Passes/StandardInstrumentations.cpp       |    8 +-
 llvm/lib/Target/AMDGPU/AMDGPU.td                   |   34 +-
 llvm/lib/Target/AMDGPU/AMDGPUGISel.td              |    4 +
 llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp      |   67 +-
 .../Target/AMDGPU/AMDGPUInstructionSelector.cpp    |   24 +-
 llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h |   10 +-
 llvm/lib/Target/AMDGPU/AMDGPUInstructions.td       |    9 +-
 llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp     |    6 +-
 .../Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp |    6 +-
 llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp         |    6 +-
 llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h           |   25 +-
 llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h |    2 +-
 llvm/lib/Target/AMDGPU/DSInstructions.td           |   76 +-
 llvm/lib/Target/AMDGPU/R600ISelLowering.cpp        |    2 +-
 llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp         |    6 +-
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp          |   90 +-
 llvm/lib/Target/AMDGPU/SIInstrInfo.cpp             |   10 +-
 llvm/lib/Target/AMDGPU/SIInstrInfo.h               |    2 +-
 llvm/lib/Target/AMDGPU/SIInstrInfo.td              |   22 +-
 llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp      |    2 +-
 llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp         |    2 +-
 llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp          |    2 +-
 llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp        |   73 +-
 llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h          |    1 -
 llvm/lib/Target/RISCV/RISCVInstrInfo.td            |    1 -
 llvm/lib/Target/RISCV/RISCVInstrInfoB.td           |   42 +-
 .../lib/Transforms/Scalar/DeadStoreElimination.cpp |    5 +
 llvm/lib/Transforms/Scalar/LoopPassManager.cpp     |    4 +-
 llvm/lib/Transforms/Utils/SimplifyCFG.cpp          |   13 +-
 llvm/test/CodeGen/AArch64/funnel-shift-rot.ll      |   24 +-
 llvm/test/CodeGen/AArch64/funnel-shift.ll          |   80 +-
 llvm/test/CodeGen/AArch64/shift-by-signext.ll      |   20 +-
 .../GlobalISel/inst-select-load-local-128.mir      |  147 +-
 .../AMDGPU/GlobalISel/legalize-load-local.mir      |  226 +-
 .../CodeGen/AMDGPU/GlobalISel/load-constant.96.ll  |    8 +-
 .../CodeGen/AMDGPU/GlobalISel/load-local.128.ll    |  300 ++
 .../CodeGen/AMDGPU/GlobalISel/load-local.96.ll     |  260 ++
 .../CodeGen/AMDGPU/GlobalISel/load-unaligned.ll    |  252 ++
 .../CodeGen/AMDGPU/GlobalISel/store-local.128.ll   |  301 ++
 .../CodeGen/AMDGPU/GlobalISel/store-local.96.ll    |  262 ++
 llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll  |   10 +-
 llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll         |    2 +-
 .../CodeGen/AMDGPU/ds-combine-with-dependence.ll   |    6 +-
 llvm/test/CodeGen/AMDGPU/ds_read2.ll               |    5 +-
 llvm/test/CodeGen/AMDGPU/ds_write2.ll              |   11 +-
 .../AMDGPU/fast-unaligned-load-store.global.ll     |    6 +-
 llvm/test/CodeGen/AMDGPU/fshl.ll                   |  274 +-
 llvm/test/CodeGen/AMDGPU/fshr.ll                   |  968 +++---
 .../AMDGPU/insert-subvector-unused-scratch.ll      |    6 +-
 llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll     |   22 +-
 llvm/test/CodeGen/AMDGPU/load-local-f32.ll         |   10 +-
 llvm/test/CodeGen/AMDGPU/load-local-i16.ll         |   12 +-
 llvm/test/CodeGen/AMDGPU/load-local-i32.ll         |    5 +-
 llvm/test/CodeGen/AMDGPU/load-local-i8.ll          |    6 +-
 llvm/test/CodeGen/AMDGPU/load-local.128.ll         |  378 +++
 llvm/test/CodeGen/AMDGPU/load-local.96.ll          |  331 ++
 llvm/test/CodeGen/AMDGPU/store-local.128.ll        |  422 +++
 llvm/test/CodeGen/AMDGPU/store-local.96.ll         |  370 +++
 llvm/test/CodeGen/AMDGPU/store-local.ll            |    5 +-
 llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll   |    2 +-
 .../AMDGPU/llc-target-cpu-attr-from-cmdline-ir.mir |    6 +-
 .../AMDGPU/llc-target-cpu-attr-from-cmdline.mir    |    4 +-
 llvm/test/CodeGen/PowerPC/fast-isel-pcrel.ll       |   73 +
 llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll      |    2 +-
 llvm/test/CodeGen/PowerPC/funnel-shift.ll          |   29 +-
 llvm/test/CodeGen/RISCV/blockaddress.ll            |    4 -
 llvm/test/CodeGen/RISCV/codemodel-lowering.ll      |   16 +-
 llvm/test/CodeGen/RISCV/indirectbr.ll              |    8 -
 llvm/test/CodeGen/RISCV/rv32Zbbp.ll                |   34 +-
 llvm/test/CodeGen/RISCV/rv32Zbt.ll                 |  467 ++-
 llvm/test/CodeGen/RISCV/rv64Zbbp.ll                |    6 +-
 llvm/test/CodeGen/RISCV/rv64Zbt.ll                 |   53 +-
 llvm/test/CodeGen/X86/fshl.ll                      |  137 +-
 llvm/test/CodeGen/X86/fshr.ll                      |  118 +-
 llvm/test/CodeGen/X86/funnel-shift.ll              |  175 +-
 llvm/test/CodeGen/X86/vector-fshl-128.ll           | 3301 ++++++++++----------
 llvm/test/CodeGen/X86/vector-fshl-256.ll           | 2543 ++++++++-------
 llvm/test/CodeGen/X86/vector-fshl-512.ll           | 1550 ++++-----
 llvm/test/CodeGen/X86/vector-fshl-rot-128.ll       |   28 +-
 llvm/test/CodeGen/X86/vector-fshr-128.ll           | 3231 +++++++++----------
 llvm/test/CodeGen/X86/vector-fshr-256.ll           | 2417 +++++++-------
 llvm/test/CodeGen/X86/vector-fshr-512.ll           | 1390 +++++----
 llvm/test/CodeGen/X86/vector-fshr-rot-128.ll       |  126 +-
 llvm/test/CodeGen/X86/vector-fshr-rot-256.ll       |   94 +-
 llvm/test/CodeGen/X86/vector-fshr-rot-512.ll       |  148 +-
 llvm/test/ObjectYAML/MachO/DWARF-debug_abbrev.yaml |   71 +-
 llvm/test/ObjectYAML/MachO/DWARF-debug_info.yaml   |  227 ++
 llvm/test/ObjectYAML/MachO/DWARF5-debug_info.yaml  |    3 +
 .../Attributor/ArgumentPromotion/X86/attributes.ll |   14 +-
 .../X86/min-legal-vector-width.ll                  |   50 +-
 .../Attributor/ArgumentPromotion/X86/thiscall.ll   |    2 +-
 .../Transforms/DeadStoreElimination/MSSA/atomic.ll |  228 +-
 .../AMDGPU/adjust-alloca-alignment.ll              |    8 +-
 .../LoadStoreVectorizer/AMDGPU/merge-stores.ll     |    5 +-
 .../LoadStoreVectorizer/AMDGPU/multiple_tails.ll   |   34 +-
 .../expander-do-not-delete-reused-values.ll        |   64 +
 .../X86/expander-reused-value-insert-point.ll      |   65 +
 .../Transforms/SimplifyCFG/ARM/phi-eliminate.ll    |  453 +++
 .../llvm-readobj/ELF/malformed-pt-dynamic.test     |   65 +-
 llvm/test/tools/llvm-readobj/ELF/merged.test       |   52 +-
 .../tools/llvm-readobj/ELF/program-headers.test    |   12 +-
 .../tools/yaml2obj/ELF/DWARF/debug-abbrev.yaml     |   25 +
 llvm/test/tools/yaml2obj/ELF/DWARF/debug-info.yaml |  101 +-
 llvm/tools/llvm-readobj/ELFDumper.cpp              |   15 +-
 llvm/tools/obj2yaml/dwarf2yaml.cpp                 |   10 +
 .../DebugInfo/DWARF/DWARFDebugInfoTest.cpp         |    1 +
 llvm/unittests/IR/PassBuilderCallbacksTest.cpp     |   76 +-
 llvm/unittests/IR/TimePassesTest.cpp               |    6 +-
 300 files changed, 16050 insertions(+), 11775 deletions(-)
 create mode 100644 clang/test/Modules/Inputs/DebugDwoId.h
 create mode 100644 clang/test/Modules/ModuleDebugInfoDwoId.cpp
 copy llvm/docs/AMDGPU/{gfx10_src32_3.rst => gfx1011_src32_2.rst} (86%)
 copy llvm/docs/AMDGPU/{gfx10_src32_2.rst => gfx1011_src32_3.rst} (82%)
 copy llvm/docs/AMDGPU/{gfx10_src32_2.rst => gfx10_src32_4.rst} (96%)
 copy llvm/docs/AMDGPU/{gfx10_src32_2.rst => gfx10_src32_5.rst} (82%)
 copy llvm/docs/AMDGPU/{gfx10_src32_3.rst => gfx10_src32_6.rst} (96%)
 copy llvm/docs/AMDGPU/{gfx10_sdata64_0.rst => gfx7_dst_buf_32.rst} (59%)
 copy llvm/docs/AMDGPU/{gfx10_sdata64_0.rst => gfx8_dst_buf_32.rst} (59%)
 copy llvm/docs/AMDGPU/{gfx8_src32_2.rst => gfx8_src32_4.rst} (96%)
 copy llvm/docs/AMDGPU/{gfx8_src32_3.rst => gfx8_src32_5.rst} (96%)
 copy llvm/docs/AMDGPU/{gfx8_src32_2.rst => gfx8_src32_6.rst} (89%)
 copy llvm/docs/AMDGPU/{gfx8_src32_3.rst => gfx8_src32_7.rst} (85%)
 copy llvm/docs/AMDGPU/{gfx9_src32_2.rst => gfx906_src32_3.rst} (89%)
 copy llvm/docs/AMDGPU/{gfx9_src32_3.rst => gfx906_src32_4.rst} (85%)
 copy llvm/docs/AMDGPU/{gfx9_src32_2.rst => gfx908_src32_4.rst} (89%)
 copy llvm/docs/AMDGPU/{gfx9_src32_3.rst => gfx908_src32_5.rst} (85%)
 copy llvm/docs/AMDGPU/{gfx9_src32_2.rst => gfx9_src32_4.rst} (96%)
 copy llvm/docs/AMDGPU/{gfx9_src32_3.rst => gfx9_src32_5.rst} (96%)
 copy llvm/docs/AMDGPU/{gfx9_src32_2.rst => gfx9_src32_6.rst} (89%)
 copy llvm/docs/AMDGPU/{gfx9_src32_3.rst => gfx9_src32_7.rst} (85%)
 create mode 100644 llvm/include/llvm/Analysis/InstCount.h
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
 create mode 100644 llvm/test/CodeGen/AMDGPU/load-local.128.ll
 create mode 100644 llvm/test/CodeGen/AMDGPU/load-local.96.ll
 create mode 100644 llvm/test/CodeGen/AMDGPU/store-local.128.ll
 create mode 100644 llvm/test/CodeGen/AMDGPU/store-local.96.ll
 create mode 100644 llvm/test/CodeGen/PowerPC/fast-isel-pcrel.ll
 create mode 100644 llvm/test/Transforms/LoopIdiom/expander-do-not-delete-reused-values.ll
 create mode 100644 llvm/test/Transforms/LoopStrengthReduce/X86/expander-reused-val [...]
 create mode 100644 llvm/test/Transforms/SimplifyCFG/ARM/phi-eliminate.ll
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[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-O3 updated (47251582f5c -> 466590192b4)