[Tcwg-commits] [binutils-gdb] branch master updated (f4b581f2d1a -> e840e61cacd)

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from f4b581f2d1a [AArch64] Update FPSR/FPCR fields for FPU and SVE new e840e61cacd opcodes/riscv: style csr names as registers

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Summary of changes: opcodes/riscv-dis.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)