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from 86654b2cc16 RISC-V: Recognized Svinval and Svnapot extensions new f556cd8bd79 RISC-V: Support load/store in mov<mode> pattern for RVV modes. new 7e924ba3474 RISC-V: ADJUST_NUNITS according to -march. new 4329d111f48 RISC-V: Fix epilogue generation for barrier.
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Summary of changes: gcc/config.gcc | 2 +- gcc/config/riscv/constraints.md | 22 ++ gcc/config/riscv/predicates.md | 23 ++ gcc/config/riscv/riscv-modes.def | 63 ++-- gcc/config/riscv/riscv-protos.h | 16 +- gcc/config/riscv/riscv-v.cc | 180 +++++++++++ gcc/config/riscv/riscv-vector-builtins-bases.cc | 14 +- gcc/config/riscv/riscv-vector-builtins.cc | 4 +- gcc/config/riscv/riscv.cc | 104 ++++-- gcc/config/riscv/riscv.h | 3 + gcc/config/riscv/riscv.md | 9 +- gcc/config/riscv/t-riscv | 4 + gcc/config/riscv/vector-iterators.md | 58 ++++ gcc/config/riscv/vector.md | 279 +++++++++++++++- gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c | 179 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c | 385 +++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c | 385 +++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c | 159 ++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c | 14 + gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c | 153 +++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c | 127 ++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c | 101 ++++++ gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c | 66 ++++ gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c | 53 ++++ gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c | 13 + gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c | 96 ++++++ gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c | 44 +++ 27 files changed, 2473 insertions(+), 83 deletions(-) create mode 100644 gcc/config/riscv/riscv-v.cc create mode 100644 gcc/config/riscv/vector-iterators.md create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c