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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk/llvm-master-arm-spec2k6-Os in repository toolchain/ci/llvm-project.
from a846427ad0a Revert "[Analysis] Link library dependencies to Analysis plugins" adds 0353e5a6cdc Permit static local structured bindings to be named from ar [...] adds e6e038c3222 [clangd] tweaks: Add clangBasic dependency to LINK_LIBS adds 3b937374469 Revert r361644, "[AMDGPU] Divergence driven ISel. Assign re [...] adds af6c9df1638 [X86][llvm-mca] Add zero idiom tests for Intel CPUs. NFC adds 4b08fcdeb13 [X86] Add zero idioms to the haswell, broadwell, and skylak [...] adds 46e5052b8e2 [X86FixupLEAs] Turn optIncDec into a generic two address LE [...] adds 17367b0d895 [LVI] Extract helper for binary range calculations; NFC adds 024b18aca7c [LVI][CVP] Calculate with.overflow result range adds 9a33dc9fb82 [CVP] Add tests for saturating add/sub ranges; NFC adds bb76cf0f964 [NFC] Update test checks adds 91131b65000 [SelectionDAG] soften assertion when legalizing narrow vect [...] adds 21498118547 [NFC] Make tests more robust for new optimizations adds 8b1fa076397 [CVP] Remove unnecessary checks for empty GNWR; NFC adds 3c7edb2de56 [LoopVectorize] Fix test by regenerating checks adds c9de92ee76f [X86] Add tests for min/maxnum with const operand; NFC adds 3f0905e46f3 [SelectionDAG] define binops as a superset of commutative binops adds 34d5a74b03f [X86][SSE] vector-sext - cleanup prefix lists adds 6bb5041e941 [LVI][CVP] Add support for saturating add/sub adds d87eceda0e6 [X86] Combine fminnum/fmaxnum with non-nan operand to fmin/fmax adds b0fd12b6892 [LLVM-C] Add Accessor for Mach-O Universal Binary Slices adds 40fa52b1749 [X86] lowerBuildVectorToBitOp - support build_vector(shift( [...] adds 0290a77aa86 [SimplifyCFG] Added condition assumption for unreachable blocks adds d4a9cae9650 Add missing newline at end of file
No new revisions were added by this update.
Summary of changes: .../clangd/refactor/tweaks/CMakeLists.txt | 1 + clang/include/clang/AST/DeclCXX.h | 12 + clang/lib/AST/DeclCXX.cpp | 6 + clang/lib/Sema/SemaExpr.cpp | 8 +- clang/lib/Serialization/ASTReaderDecl.cpp | 4 +- clang/test/CodeGenCXX/cxx1z-decomposition.cpp | 12 +- clang/test/SemaCXX/cxx1z-decomposition.cpp | 9 +- clang/unittests/Tooling/Syntax/TokensTest.cpp | 2 +- llvm/include/llvm-c/Object.h | 16 + llvm/include/llvm/CodeGen/FunctionLoweringInfo.h | 11 +- llvm/include/llvm/CodeGen/SelectionDAG.h | 1 - llvm/include/llvm/CodeGen/TargetLowering.h | 70 +- llvm/include/llvm/CodeGen/TargetRegisterInfo.h | 5 - llvm/lib/Analysis/LazyValueInfo.cpp | 98 ++- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 6 +- .../CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | 14 +- llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 33 +- llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h | 2 +- .../CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 10 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 4 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 2 +- llvm/lib/IR/ConstantRange.cpp | 3 +- llvm/lib/Object/Object.cpp | 15 + llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 142 ++-- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 91 +-- llvm/lib/Target/AMDGPU/SIISelLowering.h | 5 +- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 13 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 5 - llvm/lib/Target/ARM/ARMISelLowering.cpp | 4 +- llvm/lib/Target/ARM/ARMISelLowering.h | 3 +- llvm/lib/Target/X86/X86FixupLEAs.cpp | 154 ++-- llvm/lib/Target/X86/X86ISelLowering.cpp | 30 +- llvm/lib/Target/X86/X86SchedBroadwell.td | 87 ++- llvm/lib/Target/X86/X86SchedHaswell.td | 87 ++- llvm/lib/Target/X86/X86SchedSandyBridge.td | 20 +- llvm/lib/Target/X86/X86SchedSkylakeClient.td | 100 ++- llvm/lib/Target/X86/X86SchedSkylakeServer.td | 119 +++- .../Scalar/CorrelatedValuePropagation.cpp | 38 +- llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 3 + llvm/test/Analysis/ValueTracking/select-pattern.ll | 3 + llvm/test/CodeGen/AMDGPU/atomicrmw-nand.ll | 12 +- llvm/test/CodeGen/AMDGPU/branch-relaxation.ll | 3 +- llvm/test/CodeGen/AMDGPU/branch-uniformity.ll | 4 +- .../CodeGen/AMDGPU/control-flow-fastregalloc.ll | 7 +- .../AMDGPU/divergent-branch-uniform-condition.ll | 55 +- .../CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll | 6 +- llvm/test/CodeGen/AMDGPU/fabs.ll | 12 +- llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll | 58 +- llvm/test/CodeGen/AMDGPU/fmin_legacy.ll | 8 +- llvm/test/CodeGen/AMDGPU/fneg-fabs.ll | 16 +- llvm/test/CodeGen/AMDGPU/fsub.ll | 12 +- llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll | 10 +- .../CodeGen/AMDGPU/i1-copy-phi-uniform-branch.ll | 1 + llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll | 6 +- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll | 2 +- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.ll | 8 +- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll | 2 - .../CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll | 2 +- .../CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll | 2 +- llvm/test/CodeGen/AMDGPU/loop_break.ll | 8 +- llvm/test/CodeGen/AMDGPU/madak.ll | 12 +- .../test/CodeGen/AMDGPU/mubuf-legalize-operands.ll | 5 +- llvm/test/CodeGen/AMDGPU/multilevel-break.ll | 5 +- llvm/test/CodeGen/AMDGPU/select-opt.ll | 4 +- llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll | 3 +- llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir | 2 +- llvm/test/CodeGen/AMDGPU/smrd.ll | 1 + .../CodeGen/AMDGPU/subreg-coalescer-undef-use.ll | 53 +- .../AMDGPU/uniform-loop-inside-nonuniform.ll | 5 +- .../test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll | 9 +- llvm/test/CodeGen/AMDGPU/valu-i1.ll | 6 +- .../vgpr-spill-emergency-stack-slot-compute.ll | 1 - llvm/test/CodeGen/ARM/crash-greedy.ll | 4 +- llvm/test/CodeGen/Hexagon/bit-visit-flowq.ll | 6 +- llvm/test/CodeGen/Hexagon/rdf-ignore-undef.ll | 2 +- llvm/test/CodeGen/Hexagon/reg-scavengebug.ll | 4 +- .../test/CodeGen/Hexagon/regalloc-block-overlap.ll | 4 +- llvm/test/CodeGen/PowerPC/ftrunc-legalize.ll | 24 + llvm/test/CodeGen/X86/GlobalISel/add-ext.ll | 12 +- llvm/test/CodeGen/X86/GlobalISel/callingconv.ll | 2 +- llvm/test/CodeGen/X86/GlobalISel/gep.ll | 14 +- llvm/test/CodeGen/X86/GlobalISel/memop-scalar.ll | 2 +- llvm/test/CodeGen/X86/MergeConsecutiveStores.ll | 4 +- llvm/test/CodeGen/X86/atomic-unordered.ll | 2 +- .../CodeGen/X86/avx512vl-intrinsics-upgrade.ll | 12 +- llvm/test/CodeGen/X86/bitreverse.ll | 4 +- llvm/test/CodeGen/X86/bswap_tree2.ll | 2 +- llvm/test/CodeGen/X86/bypass-slow-division-32.ll | 2 +- llvm/test/CodeGen/X86/combine-srem.ll | 2 +- llvm/test/CodeGen/X86/dagcombine-shifts.ll | 4 +- llvm/test/CodeGen/X86/extract-fp.ll | 20 +- llvm/test/CodeGen/X86/fixup-bw-copy.ll | 2 +- llvm/test/CodeGen/X86/fixup-lea.ll | 4 +- llvm/test/CodeGen/X86/fmaxnum.ll | 28 + llvm/test/CodeGen/X86/fminnum.ll | 28 + llvm/test/CodeGen/X86/horizontal-reduce-smax.ll | 44 +- llvm/test/CodeGen/X86/horizontal-reduce-smin.ll | 44 +- llvm/test/CodeGen/X86/horizontal-reduce-umax.ll | 44 +- llvm/test/CodeGen/X86/horizontal-reduce-umin.ll | 44 +- llvm/test/CodeGen/X86/imul.ll | 10 +- llvm/test/CodeGen/X86/leaFixup32.mir | 2 +- llvm/test/CodeGen/X86/leaFixup64.mir | 4 +- llvm/test/CodeGen/X86/mul-constant-i16.ll | 2 +- llvm/test/CodeGen/X86/mul-constant-i32.ll | 4 +- llvm/test/CodeGen/X86/mul-constant-i64.ll | 26 +- llvm/test/CodeGen/X86/mul-constant-i8.ll | 2 +- llvm/test/CodeGen/X86/popcnt.ll | 6 +- llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll | 2 +- llvm/test/CodeGen/X86/reverse_branches.ll | 2 +- llvm/test/CodeGen/X86/rotate-extract-vector.ll | 9 +- llvm/test/CodeGen/X86/rotate-extract.ll | 4 +- llvm/test/CodeGen/X86/sat-add.ll | 6 +- llvm/test/CodeGen/X86/twoaddr-lea.ll | 2 +- llvm/test/CodeGen/X86/vector-bitreverse.ll | 4 +- llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll | 9 +- llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll | 25 +- llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll | 9 +- llvm/test/CodeGen/X86/vector-reduce-smax-widen.ll | 111 +-- llvm/test/CodeGen/X86/vector-reduce-smax.ll | 111 +-- llvm/test/CodeGen/X86/vector-reduce-smin-widen.ll | 111 +-- llvm/test/CodeGen/X86/vector-reduce-smin.ll | 111 +-- llvm/test/CodeGen/X86/vector-reduce-umax-widen.ll | 111 +-- llvm/test/CodeGen/X86/vector-reduce-umax.ll | 111 +-- llvm/test/CodeGen/X86/vector-reduce-umin-widen.ll | 111 +-- llvm/test/CodeGen/X86/vector-reduce-umin.ll | 111 +-- llvm/test/CodeGen/X86/vector-sext-widen.ll | 120 ++-- llvm/test/CodeGen/X86/vector-sext.ll | 120 ++-- llvm/test/CodeGen/X86/win_coreclr_chkstk.ll | 2 +- .../Transforms/CallSiteSplitting/split-loop.ll | 24 +- .../Transforms/CorrelatedValuePropagation/basic.ll | 97 +++ .../overflow_predicate.ll | 21 +- .../LoopStrengthReduce/X86/ivchain-X86.ll | 8 +- .../Transforms/LoopVectorize/if-pred-stores.ll | 532 +++++++++++--- llvm/test/Transforms/SimplifyCFG/PR30210.ll | 14 +- .../Transforms/SimplifyCFG/UnreachableEliminate.ll | 141 ++-- .../Transforms/SimplifyCFG/unreachable_assume.ll | 46 ++ .../tools/llvm-mca/X86/Broadwell/zero-idioms.s | 450 ++++++++++++ llvm/test/tools/llvm-mca/X86/Haswell/zero-idioms.s | 492 +++++++++++++ .../tools/llvm-mca/X86/SandyBridge/zero-idioms.s | 128 ++-- .../tools/llvm-mca/X86/SkylakeClient/zero-idioms.s | 492 +++++++++++++ .../tools/llvm-mca/X86/SkylakeServer/zero-idioms.s | 778 +++++++++++++++++++++ 141 files changed, 4906 insertions(+), 1527 deletions(-) create mode 100644 llvm/test/CodeGen/PowerPC/ftrunc-legalize.ll create mode 100644 llvm/test/Transforms/SimplifyCFG/unreachable_assume.ll create mode 100644 llvm/test/tools/llvm-mca/X86/Broadwell/zero-idioms.s create mode 100644 llvm/test/tools/llvm-mca/X86/Haswell/zero-idioms.s create mode 100644 llvm/test/tools/llvm-mca/X86/SkylakeClient/zero-idioms.s create mode 100644 llvm/test/tools/llvm-mca/X86/SkylakeServer/zero-idioms.s