[Tcwg-commits] [gcc] branch master updated (af595613acb -> 44564a4ab7b)

11 May 2023


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in repository gcc.
from  af595613acb libstdc++: Fix std::abs(__float128) for -NaN and -0.0 [PR109758]
       new  b75c9e10379 RISC-V: Add vectorized binops and insn_expander helpers.
       new  84d2899638a RISC-V: Clarify vlmax and length handling.
       new  8c08201f06e RISC-V: Split off shift patterns for autovectorization.
       new  6cb594f3ffc RISC-V: Add autovectorization tests for binary integer operations.
       new  44564a4ab7b RISC-V: Update RVV integer compare simplification comments
The 5 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
 gcc/config/riscv/autovec.md                        |  90 +++++++++-
 gcc/config/riscv/riscv-protos.h                    |   6 +-
 gcc/config/riscv/riscv-v.cc                        | 192 +++++++++++++--------
 gcc/config/riscv/riscv.cc                          |   4 +-
 gcc/config/riscv/vector-iterators.md               |   4 +
 gcc/config/riscv/vector.md                         |  21 ++-
 .../riscv/rvv/autovec/shift-run-template.h}        |   0
 .../gcc.target/riscv/rvv/autovec/shift-run.c       |  52 ++++++
 .../gcc.target/riscv/rvv/autovec/shift-rv32gcv.c   |  11 ++
 .../gcc.target/riscv/rvv/autovec/shift-rv64gcv.c   |  11 ++
 .../riscv/rvv/autovec/shift-scalar-run.c           |   4 +
 .../riscv/rvv/autovec/shift-scalar-rv32gcv.c       |   7 +
 .../riscv/rvv/autovec/shift-scalar-rv64gcv.c       |   7 +
 .../riscv/rvv/autovec/shift-scalar-template.h      | 119 +++++++++++++
 .../gcc.target/riscv/rvv/autovec/shift-template.h  |  34 ++++
 .../riscv/rvv/autovec/vadd-run-template.h}         |   0
 .../gcc.target/riscv/rvv/autovec/vadd-run.c        |  69 ++++++++
 .../gcc.target/riscv/rvv/autovec/vadd-rv32gcv.c    |   7 +
 .../gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c    |   7 +
 .../gcc.target/riscv/rvv/autovec/vadd-template.h   |  56 ++++++
 .../riscv/rvv/autovec/vand-run-template.h}         |   0
 .../gcc.target/riscv/rvv/autovec/vand-run.c        |  69 ++++++++
 .../gcc.target/riscv/rvv/autovec/vand-rv32gcv.c    |   7 +
 .../gcc.target/riscv/rvv/autovec/vand-rv64gcv.c    |   7 +
 .../gcc.target/riscv/rvv/autovec/vand-template.h   |  56 ++++++
 .../riscv/rvv/autovec/vdiv-run-template.h}         |   0
 .../gcc.target/riscv/rvv/autovec/vdiv-run.c        |  47 +++++
 .../gcc.target/riscv/rvv/autovec/vdiv-rv32gcv.c    |   9 +
 .../gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c    |   9 +
 .../gcc.target/riscv/rvv/autovec/vdiv-template.h   |  34 ++++
 .../riscv/rvv/autovec/vmax-run-template.h}         |   0
 .../gcc.target/riscv/rvv/autovec/vmax-run.c        |  47 +++++
 .../gcc.target/riscv/rvv/autovec/vmax-rv32gcv.c    |   7 +
 .../gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c    |   7 +
 .../gcc.target/riscv/rvv/autovec/vmax-template.h   |  34 ++++
 .../riscv/rvv/autovec/vmin-run-template.h}         |   0
 .../gcc.target/riscv/rvv/autovec/vmin-run.c        |  47 +++++
 .../gcc.target/riscv/rvv/autovec/vmin-rv32gcv.c    |   7 +
 .../gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c    |   7 +
 .../gcc.target/riscv/rvv/autovec/vmin-template.h   |  34 ++++
 .../riscv/rvv/autovec/vmul-run-template.h}         |   0
 .../gcc.target/riscv/rvv/autovec/vmul-run.c        |  47 +++++
 .../gcc.target/riscv/rvv/autovec/vmul-rv32gcv.c    |   6 +
 .../gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c    |   6 +
 .../gcc.target/riscv/rvv/autovec/vmul-template.h   |  34 ++++
 .../riscv/rvv/autovec/vor-run-template.h}          |   0
 .../gcc.target/riscv/rvv/autovec/vor-run.c         |  69 ++++++++
 .../gcc.target/riscv/rvv/autovec/vor-rv32gcv.c     |   7 +
 .../gcc.target/riscv/rvv/autovec/vor-rv64gcv.c     |   7 +
 .../gcc.target/riscv/rvv/autovec/vor-template.h    |  56 ++++++
 .../riscv/rvv/autovec/vrem-run-template.h}         |   0
 .../gcc.target/riscv/rvv/autovec/vrem-run.c        |  47 +++++
 .../gcc.target/riscv/rvv/autovec/vrem-rv32gcv.c    |   9 +
 .../gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c    |   9 +
 .../gcc.target/riscv/rvv/autovec/vrem-template.h   |  34 ++++
 .../riscv/rvv/autovec/vsub-run-template.h}         |   0
 .../gcc.target/riscv/rvv/autovec/vsub-run.c        |  47 +++++
 .../gcc.target/riscv/rvv/autovec/vsub-rv32gcv.c    |   6 +
 .../gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c    |   6 +
 .../gcc.target/riscv/rvv/autovec/vsub-template.h   |  34 ++++
 .../riscv/rvv/autovec/vxor-run-template.h}         |   0
 .../gcc.target/riscv/rvv/autovec/vxor-run.c        |  69 ++++++++
 .../gcc.target/riscv/rvv/autovec/vxor-rv32gcv.c    |   7 +
 .../gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c    |   7 +
 .../gcc.target/riscv/rvv/autovec/vxor-template.h   |  56 ++++++
 65 files changed, 1602 insertions(+), 90 deletions(-)
 copy gcc/{config/i386/t-cygwin-w64 => testsuite/gcc.target/riscv/rvv/autovec/shift [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-run.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv32gcv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv64gcv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-run.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-rv32gcv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-template.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-template.h
 copy gcc/{config/i386/t-cygwin-w64 => testsuite/gcc.target/riscv/rvv/autovec/vadd- [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-run.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv32gcv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-template.h
 copy gcc/{config/i386/t-cygwin-w64 => testsuite/gcc.target/riscv/rvv/autovec/vand- [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-run.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv32gcv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv64gcv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-template.h
 copy gcc/{config/i386/t-cygwin-w64 => testsuite/gcc.target/riscv/rvv/autovec/vdiv- [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-run.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv32gcv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-template.h
 copy gcc/{config/i386/t-cygwin-w64 => testsuite/gcc.target/riscv/rvv/autovec/vmax- [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-run.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv32gcv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-template.h
 copy gcc/{config/i386/t-cygwin-w64 => testsuite/gcc.target/riscv/rvv/autovec/vmin- [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-run.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv32gcv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-template.h
 copy gcc/{config/i386/t-cygwin-w64 => testsuite/gcc.target/riscv/rvv/autovec/vmul- [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-run.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv32gcv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-template.h
 copy gcc/{config/i386/t-cygwin-w64 => testsuite/gcc.target/riscv/rvv/autovec/vor-r [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-run.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv32gcv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv64gcv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-template.h
 copy gcc/{config/i386/t-cygwin-w64 => testsuite/gcc.target/riscv/rvv/autovec/vrem- [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-run.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv32gcv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-template.h
 copy gcc/{config/i386/t-cygwin-w64 => testsuite/gcc.target/riscv/rvv/autovec/vsub- [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-run.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv32gcv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-template.h
 copy gcc/{config/i386/t-cygwin-w64 => testsuite/gcc.target/riscv/rvv/autovec/vxor- [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-run.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv32gcv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-template.h
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[Tcwg-commits] [gcc] branch master updated (af595613acb -> 44564a4ab7b)