[Tcwg-commits] [llvm] branch master updated (734bf57ca87 -> 91902636932)

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from 734bf57ca87 [DAGCombiner] Combine OR as ADD when no common bits are set new 91902636932 Fix MSVC "32-bit shift implicitly converted to 64 bits" war [...]

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Summary of changes: lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)