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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-allnoconfig in repository toolchain/ci/qemu.
from 7adb961995 Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/p [...] adds 5690b4370b python: Update for pylint 2.10 adds eb8033f658 python: pylint 2.11 support adds c3f76fbca6 Merge remote-tracking branch 'remotes/jsnow-gitlab/tags/pyth [...] adds 080832e4f4 ebpf: only include in system emulators adds bedd7e93d0 virtio-net: fix use after unmap/free for sg adds 326ff8dd09 Merge remote-tracking branch 'remotes/jasowang/tags/net-pull [...] adds 2919328639 hw: arm: aspeed: Enable eth0 interface for aspeed-ast2600-evb adds 5bb825c835 hw: arm: aspeed: Enable mac0/1 instead of mac1/2 for g220a adds 709098fd37 watchdog: aspeed: Sanitize control register values adds 74b67e1f9d watchdog: aspeed: Fix sequential control writes adds 64e5758b75 hw: aspeed_gpio: Simplify 1.8V defines adds 98edb134c3 hw: aspeed_gpio: Clarify GPIO controller name adds 0c33a48df4 misc/pca9552: Fix LED status register indexing in pca955x_get_led() adds fa6d98c060 arm/aspeed: rainier: Add i2c eeproms and muxes adds c5811bb3b7 aspeed: Emulate the AST2600A3 adds 46560cb105 hw/misc: Add Infineon DPS310 sensor model adds b61ea6e7df arm/aspeed: Add DPS310 to Witherspoon and Rainier adds 9dca455683 hw/arm/aspeed: Initialize AST2600 UART clock selection registers adds 5d63d0c76c hw/arm/aspeed: Allow machine to set UART default adds febbe308bf hw/arm/aspeed: Add Fuji machine type adds 1c81a38c5a Merge remote-tracking branch 'remotes/legoater/tags/pull-asp [...] adds e59a7e0ec5 elf2dmp: Check curl_easy_setopt() return value adds f015cbb546 elf2dmp: Fail cleanly if PDB file specifies zero block_size adds b62ceeaf80 target/arm: Don't skip M-profile reset entirely in user mode adds 4a888072c8 target/arm: Always clear exclusive monitor on reset adds 1426f2449e target/arm: Consolidate ifdef blocks in reset adds 9cee1efe92 hw/intc: Set GIC maintenance interrupt level to only 0 or 1 adds 0130895ddf arm: Move PMC register definitions to internals.h adds 5b3e751724 hvf: Add execute to dirty log permission bitmap adds ce7f5b1c50 hvf: Introduce hvf_arch_init() callback adds a1477da3dd hvf: Add Apple Silicon support adds 219c101fa7 arm/hvf: Add a WFI handler adds 585df85efe hvf: arm: Implement -cpu host adds 2c9c0bf9d1 hvf: arm: Implement PSCI handling adds 844a06bbe4 arm: Add Hypervisor.framework build target adds dd43ac07ef hvf: arm: Add rudimentary PMC support adds 84848481c3 target/arm: Avoid goto_tb if we're trying to exit to the main loop adds 85e7d1e9ff target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration adds 2670221397 target/arm: Add TB flag for "MVE insns not predicated" adds 451f9d66cf target/arm: Optimize MVE logic ops adds bc3087f253 target/arm: Optimize MVE arithmetic ops adds 4b1561c472 target/arm: Optimize MVE VNEG, VABS adds f8d94803f1 target/arm: Optimize MVE VDUP adds 5cf525a8a6 target/arm: Optimize MVE VMVN adds 752970ef7c target/arm: Optimize MVE VSHL, VSHR immediate forms adds a7789fabe1 target/arm: Optimize MVE VSHLL and VMOVL adds ce75c43f6d target/arm: Optimize MVE VSLI and VSRI adds 4b445c926a target/arm: Optimize MVE 1op-immediate insns adds 81ceb36b96 Merge remote-tracking branch 'remotes/pmaydell/tags/pull-tar [...] adds a44da25aa6 target/riscv: Update the ePMP CSR address adds 15732b8ed2 target/riscv: Fix satp write adds 0f0b70eeec target/riscv: Expose interrupt pending bits as GPIO lines adds a714b8aa02 hw/intc: sifive_clint: Use RISC-V CPU GPIO lines adds e5cc6aaeb5 hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines adds f436ecc315 hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines adds 57a3a62265 hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines adds 5bf6f1acdd hw/timer: Add SiFive PWM support adds ea6eaa0604 sifive_u: Connect the SiFive PWM device adds cc63a18282 hw/intc: Rename sifive_clint sources to riscv_aclint sources adds b8fb878aa2 hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT adds 0ffc1a9522 hw/riscv: virt: Re-factor FDT generation adds 954886ea6d hw/riscv: virt: Add optional ACLINT support to virt machine adds de7c7988d2 hw/dma: sifive_pdma: reset Next* registers when Control.clai [...] adds 9a8c26c08c hw/dma: sifive_pdma: claim bit must be set before DMA transactions adds e22d90f5f9 hw/dma: sifive_pdma: allow non-multiple transaction size tra [...] adds ae000c5f65 hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer adds 758c07c9fc docs/system/riscv: sifive_u: Update U-Boot instructions adds c601354756 target/riscv: Backup/restore mstatus.SD bit when virtual reg [...] adds db70794ea8 target/riscv: csr: Rename HCOUNTEREN_CY and friends adds ed481d9837 hw/riscv: opentitan: Correct the USB Dev address adds 2c3e83f92d Merge remote-tracking branch 'remotes/alistair23/tags/pull-r [...]
No new revisions were added by this update.
Summary of changes: MAINTAINERS | 5 + accel/hvf/hvf-accel-ops.c | 21 +- contrib/elf2dmp/download.c | 22 +- contrib/elf2dmp/pdb.c | 4 + docs/system/riscv/sifive_u.rst | 50 +- docs/system/riscv/virt.rst | 10 + ebpf/meson.build | 2 +- hw/arm/Kconfig | 1 + hw/arm/aspeed.c | 182 ++- hw/arm/aspeed_ast2600.c | 14 +- hw/arm/aspeed_soc.c | 8 +- hw/dma/sifive_pdma.c | 54 +- hw/gpio/aspeed_gpio.c | 97 +- hw/intc/Kconfig | 2 +- hw/intc/arm_gicv3_cpuif.c | 5 +- hw/intc/ibex_plic.c | 17 +- hw/intc/meson.build | 2 +- hw/intc/riscv_aclint.c | 460 +++++++ hw/intc/sifive_clint.c | 287 ----- hw/intc/sifive_plic.c | 30 +- hw/misc/aspeed_scu.c | 40 +- hw/misc/pca9552.c | 2 +- hw/net/virtio-net.c | 39 +- hw/riscv/Kconfig | 13 +- hw/riscv/microchip_pfsoc.c | 13 +- hw/riscv/opentitan.c | 13 +- hw/riscv/shakti_c.c | 16 +- hw/riscv/sifive_e.c | 15 +- hw/riscv/sifive_u.c | 68 +- hw/riscv/spike.c | 16 +- hw/riscv/virt.c | 654 ++++++---- hw/sensor/Kconfig | 4 + hw/sensor/dps310.c | 225 ++++ hw/sensor/meson.build | 1 + hw/timer/Kconfig | 3 + hw/timer/ibex_timer.c | 17 +- hw/timer/meson.build | 1 + hw/timer/sifive_pwm.c | 468 +++++++ hw/timer/trace-events | 6 + hw/watchdog/wdt_aspeed.c | 26 +- include/hw/arm/aspeed.h | 1 + include/hw/arm/aspeed_soc.h | 1 + include/hw/intc/ibex_plic.h | 2 + include/hw/intc/riscv_aclint.h | 80 ++ include/hw/intc/sifive_clint.h | 60 - include/hw/intc/sifive_plic.h | 4 + include/hw/misc/aspeed_scu.h | 2 + include/hw/riscv/sifive_u.h | 14 +- include/hw/riscv/virt.h | 2 + include/hw/timer/ibex_timer.h | 2 + .../stm32f4xx_syscfg.h => timer/sifive_pwm.h} | 48 +- include/hw/watchdog/wdt_aspeed.h | 1 + include/sysemu/hvf_int.h | 12 +- meson.build | 8 + python/qemu/machine/machine.py | 7 +- python/setup.cfg | 3 +- target/arm/cpu.c | 56 +- target/arm/cpu.h | 6 +- target/arm/helper.c | 77 +- target/arm/hvf/hvf.c | 1278 ++++++++++++++++++++ target/arm/hvf/meson.build | 3 + target/arm/hvf/trace-events | 11 + target/arm/hvf_arm.h | 18 + target/arm/internals.h | 44 + target/arm/kvm_arm.h | 2 - target/arm/machine.c | 13 + target/arm/meson.build | 2 + target/arm/translate-m-nocp.c | 8 +- target/arm/translate-mve.c | 310 +++-- target/arm/translate-vfp.c | 33 +- target/arm/translate.c | 42 +- target/arm/translate.h | 2 + target/i386/hvf/hvf.c | 11 + target/riscv/cpu.c | 31 + target/riscv/cpu_bits.h | 12 +- target/riscv/cpu_helper.c | 3 +- target/riscv/csr.c | 26 +- 77 files changed, 4202 insertions(+), 946 deletions(-) create mode 100644 hw/intc/riscv_aclint.c delete mode 100644 hw/intc/sifive_clint.c create mode 100644 hw/sensor/dps310.c create mode 100644 hw/timer/sifive_pwm.c create mode 100644 include/hw/intc/riscv_aclint.h delete mode 100644 include/hw/intc/sifive_clint.h copy include/hw/{misc/stm32f4xx_syscfg.h => timer/sifive_pwm.h} (60%) create mode 100644 target/arm/hvf/hvf.c create mode 100644 target/arm/hvf/meson.build create mode 100644 target/arm/hvf/trace-events create mode 100644 target/arm/hvf_arm.h