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from b602cf0752d [AArch64] Add v8.5-a Memory Tagging GMID_EL1 register new 2e53035953b [RISCV] Generate address sequences suitable for mcmodel=medium
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Summary of changes: include/llvm/CodeGen/MachineBasicBlock.h | 11 ++++ lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 5 +- lib/Target/RISCV/RISCVExpandPseudoInsts.cpp | 45 +++++++++++++++ lib/Target/RISCV/RISCVISelLowering.cpp | 88 +++++++++++++++++------------ lib/Target/RISCV/RISCVISelLowering.h | 4 ++ lib/Target/RISCV/RISCVInstrInfo.cpp | 1 + lib/Target/RISCV/RISCVMCInstLower.cpp | 6 ++ lib/Target/RISCV/Utils/RISCVBaseInfo.h | 1 + test/CodeGen/RISCV/codemodel-lowering.ll | 80 ++++++++++++++++++++++++++ 9 files changed, 205 insertions(+), 36 deletions(-) create mode 100644 test/CodeGen/RISCV/codemodel-lowering.ll