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from d55d40afd42 LoongArch: Optimize for conditional move operations new 55f31c715f7 RISC-V: Add testcases for unsigned imm vec SAT_SUB form2~4
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Summary of changes: .../riscv/rvv/autovec/sat/vec_sat_arith.h | 54 +++++ .../riscv/rvv/autovec/sat/vec_sat_data.h | 256 +++++++++++++++++++-- ...sat_u_sub-1-u16.c => vec_sat_u_sub_imm-2-u16.c} | 2 +- ...sat_u_sub-1-u16.c => vec_sat_u_sub_imm-2-u32.c} | 2 +- ...sat_u_sub-1-u16.c => vec_sat_u_sub_imm-2-u64.c} | 2 +- ..._sat_u_sub-1-u16.c => vec_sat_u_sub_imm-2-u8.c} | 2 +- ...sat_u_sub-1-u16.c => vec_sat_u_sub_imm-3-u16.c} | 2 +- ...sat_u_sub-1-u16.c => vec_sat_u_sub_imm-3-u32.c} | 2 +- ...sat_u_sub-1-u16.c => vec_sat_u_sub_imm-3-u64.c} | 2 +- ..._sat_u_sub-1-u16.c => vec_sat_u_sub_imm-3-u8.c} | 2 +- ...sat_u_sub-1-u16.c => vec_sat_u_sub_imm-4-u16.c} | 2 +- ...sat_u_sub-1-u16.c => vec_sat_u_sub_imm-4-u32.c} | 2 +- ...sat_u_sub-1-u16.c => vec_sat_u_sub_imm-4-u64.c} | 2 +- ..._sat_u_sub-1-u16.c => vec_sat_u_sub_imm-4-u8.c} | 2 +- .../rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u16.c | 28 +++ .../rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u32.c | 28 +++ .../rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u64.c | 28 +++ .../rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u8.c | 28 +++ ...m-run-1-u16.c => vec_sat_u_sub_imm-run-3-u16.c} | 10 +- ...m-run-1-u32.c => vec_sat_u_sub_imm-run-3-u32.c} | 10 +- ...m-run-1-u64.c => vec_sat_u_sub_imm-run-3-u64.c} | 10 +- ...imm-run-1-u8.c => vec_sat_u_sub_imm-run-3-u8.c} | 10 +- .../rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u16.c | 28 +++ .../rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u32.c | 28 +++ .../rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u64.c | 28 +++ .../rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u8.c | 28 +++ 26 files changed, 550 insertions(+), 48 deletions(-) copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_sub-1-u16.c => vec_ [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_sub-1-u16.c => vec_ [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_sub-1-u16.c => vec_ [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_sub-1-u16.c => vec_ [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_sub-1-u16.c => vec_ [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_sub-1-u16.c => vec_ [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_sub-1-u16.c => vec_ [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_sub-1-u16.c => vec_ [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_sub-1-u16.c => vec_ [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_sub-1-u16.c => vec_ [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_sub-1-u16.c => vec_ [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_sub-1-u16.c => vec_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_im [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_im [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_im [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_im [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_sub_imm-run-1-u16.c [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_sub_imm-run-1-u32.c [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_sub_imm-run-1-u64.c [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_sub_imm-run-1-u8.c [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_im [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_im [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_im [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_im [...]