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from 18f599f81e9 [llvm-readobj] - Refactor the code. new bac41ae77dc [LoopUnroll] Use LoopSize+1 as threshold, to allow unrollin [...] new 1bff644c7fa [ARM] LE support in ConstantIslands new 7ae04842e06 [AMDGPU]: PHI Elimination hooks added for custom COPY inser [...] new efc29761d18 [llvm-readobj] - Fix a TODO in elf-reloc-zero-name-or-value.test.
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Summary of changes: include/llvm/CodeGen/TargetInstrInfo.h | 23 +++ lib/CodeGen/PHIElimination.cpp | 28 +-- lib/Target/AMDGPU/SIInstrInfo.cpp | 37 ++++ lib/Target/AMDGPU/SIInstrInfo.h | 13 ++ lib/Target/AMDGPU/SILowerControlFlow.cpp | 49 +++-- lib/Target/ARM/ARMConstantIslandPass.cpp | 137 +++++++++++--- lib/Transforms/Scalar/LoopUnrollPass.cpp | 6 +- test/CodeGen/AMDGPU/phi-elimination-assertion.mir | 2 +- test/CodeGen/AMDGPU/phi-elimination-end-cf.mir | 54 ++++++ test/CodeGen/ARM/O3-pipeline.ll | 2 +- .../Thumb2/LowOverheadLoops/no-dec-cbnz.mir | 201 +++++++++++++++++++++ .../Thumb2/LowOverheadLoops/no-dec-le-simple.ll | 158 ++++++++++++++++ .../Thumb2/LowOverheadLoops/no-dec-reorder.mir | 184 +++++++++++++++++++ test/CodeGen/Thumb2/LowOverheadLoops/no-dec.mir | 201 +++++++++++++++++++++ .../LoopUnroll/AArch64/unroll-optsize.ll | 4 +- test/Transforms/LoopUnroll/optsize-loop-size.ll | 58 ++++++ .../llvm-readobj/elf-reloc-zero-name-or-value.test | 26 ++- 17 files changed, 1115 insertions(+), 68 deletions(-) create mode 100644 test/CodeGen/AMDGPU/phi-elimination-end-cf.mir create mode 100644 test/CodeGen/Thumb2/LowOverheadLoops/no-dec-cbnz.mir create mode 100644 test/CodeGen/Thumb2/LowOverheadLoops/no-dec-le-simple.ll create mode 100644 test/CodeGen/Thumb2/LowOverheadLoops/no-dec-reorder.mir create mode 100644 test/CodeGen/Thumb2/LowOverheadLoops/no-dec.mir create mode 100644 test/Transforms/LoopUnroll/optsize-loop-size.ll