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from fbd7c49bba4 aarch64: Remove cmov<mode>6 patterns new 656db31e444 Match: Support form 7 for unsigned integer SAT_ADD new f6535d433e2 RISC-V: Add testcases for scalar unsigned integer SAT_ADD form 7 new c273a1c1846 RISC-V: Add testcases for vector unsigned integer SAT_ADD form 7
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Summary of changes: gcc/match.pd | 16 ++++++++++- .../riscv/rvv/autovec/sat/vec_sat_arith.h | 31 ++++++++++++++++++++++ ..._add-1-u32.c => vec_sat_u_add-9-u16-from-u32.c} | 2 +- ..._add-1-u32.c => vec_sat_u_add-9-u16-from-u64.c} | 2 +- ..._add-1-u32.c => vec_sat_u_add-9-u32-from-u64.c} | 2 +- ...u_add-1-u32.c => vec_sat_u_add-9-u8-from-u16.c} | 2 +- ...u_add-1-u32.c => vec_sat_u_add-9-u8-from-u32.c} | 2 +- ...u_add-1-u32.c => vec_sat_u_add-9-u8-from-u64.c} | 2 +- ...-1-u16.c => vec_sat_u_add-run-9-u16-from-u32.c} | 5 ++-- ...-3-u16.c => vec_sat_u_add-run-9-u16-from-u64.c} | 5 ++-- ...-2-u32.c => vec_sat_u_add-run-9-u32-from-u64.c} | 5 ++-- ...un-2-u8.c => vec_sat_u_add-run-9-u8-from-u16.c} | 5 ++-- ...un-3-u8.c => vec_sat_u_add-run-9-u8-from-u32.c} | 5 ++-- ...un-2-u8.c => vec_sat_u_add-run-9-u8-from-u64.c} | 5 ++-- gcc/testsuite/gcc.target/riscv/sat/sat_arith.h | 22 +++++++++++++++ ...at_u_add-1-u16.c => sat_u_add-7-u16-from-u32.c} | 4 +-- ...at_u_add-1-u16.c => sat_u_add-7-u16-from-u64.c} | 4 +-- ...at_u_add-2-u32.c => sat_u_add-7-u32-from-u64.c} | 4 +-- ...{sat_u_add-3-u8.c => sat_u_add-7-u8-from-u16.c} | 4 +-- ...{sat_u_add-3-u8.c => sat_u_add-7-u8-from-u32.c} | 4 +-- ...{sat_u_add-3-u8.c => sat_u_add-7-u8-from-u64.c} | 4 +-- ...-run-1-u16.c => sat_u_add-run-7-u16-from-u32.c} | 5 ++-- ...-run-1-u16.c => sat_u_add-run-7-u16-from-u64.c} | 5 ++-- ...-run-2-u32.c => sat_u_add-run-7-u32-from-u64.c} | 5 ++-- ...dd-run-3-u8.c => sat_u_add-run-7-u8-from-u16.c} | 5 ++-- ...dd-run-3-u8.c => sat_u_add-run-7-u8-from-u32.c} | 5 ++-- ...dd-run-3-u8.c => sat_u_add-run-7-u8-from-u64.c} | 5 ++-- 27 files changed, 122 insertions(+), 43 deletions(-) copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_add-1-u32.c => vec_ [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_add-1-u32.c => vec_ [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_add-1-u32.c => vec_ [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_add-1-u32.c => vec_ [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_add-1-u32.c => vec_ [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_add-1-u32.c => vec_ [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_add-run-1-u16.c => [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_add-run-3-u16.c => [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_add-run-2-u32.c => [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_add-run-2-u8.c => v [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_add-run-3-u8.c => v [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_add-run-2-u8.c => v [...] copy gcc/testsuite/gcc.target/riscv/sat/{sat_u_add-1-u16.c => sat_u_add-7-u16-from [...] copy gcc/testsuite/gcc.target/riscv/sat/{sat_u_add-1-u16.c => sat_u_add-7-u16-from [...] copy gcc/testsuite/gcc.target/riscv/sat/{sat_u_add-2-u32.c => sat_u_add-7-u32-from [...] copy gcc/testsuite/gcc.target/riscv/sat/{sat_u_add-3-u8.c => sat_u_add-7-u8-from-u [...] copy gcc/testsuite/gcc.target/riscv/sat/{sat_u_add-3-u8.c => sat_u_add-7-u8-from-u [...] copy gcc/testsuite/gcc.target/riscv/sat/{sat_u_add-3-u8.c => sat_u_add-7-u8-from-u [...] copy gcc/testsuite/gcc.target/riscv/sat/{sat_u_add-run-1-u16.c => sat_u_add-run-7- [...] copy gcc/testsuite/gcc.target/riscv/sat/{sat_u_add-run-1-u16.c => sat_u_add-run-7- [...] copy gcc/testsuite/gcc.target/riscv/sat/{sat_u_add-run-2-u32.c => sat_u_add-run-7- [...] copy gcc/testsuite/gcc.target/riscv/sat/{sat_u_add-run-3-u8.c => sat_u_add-run-7-u [...] copy gcc/testsuite/gcc.target/riscv/sat/{sat_u_add-run-3-u8.c => sat_u_add-run-7-u [...] copy gcc/testsuite/gcc.target/riscv/sat/{sat_u_add-run-3-u8.c => sat_u_add-run-7-u [...]