Tcwg-commits July 2025

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[linux-next] branch fs-current updated (ee48bffd151f -> 94c386fc5659)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch fs-current in repository linux-next. omits ee48bffd151f Merge branch 'next-fixes' of git://git.kernel.org/pub/scm/ [...] omits 1853217305ff Merge branch 'vfs.fixes' of git://git.kernel.org/pub/scm/l [...] new b1bf1a782fdf dm-bufio: fix sched in atomic context new 155a3c003e55 Merge tag 'for-6.16/dm-fixes-2' of git://git.kernel.org/pu [...] new 807a55cb4239 Merge branch 'vfs.fixes' of git://git.kernel.org/pub/scm/l [...] new 94c386fc5659 Merge branch 'next-fixes' of git://git.kernel.org/pub/scm/ [...] This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (ee48bffd151f) \ N -- N -- N refs/heads/fs-current (94c386fc5659) You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 4 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: drivers/md/dm-bufio.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 weeks, 3 days

[gcc] branch master updated (7b716c7afec -> 2b19a1ccbc0)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 7b716c7afec Daily bump. new 430be3b933b RISC-V: Support RVVDImode for avg3_floor auto vect new 2b19a1ccbc0 RISC-V: Refine the scalar SAT_* test cases The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/riscv/autovec.md | 13 ++++++ gcc/testsuite/gcc.target/riscv/rvv/autovec/avg.h | 5 +++ .../rvv/autovec/avg_ceil-run-1-i16-from-i32.c | 2 +- .../rvv/autovec/avg_ceil-run-1-i16-from-i64.c | 2 +- .../rvv/autovec/avg_ceil-run-1-i32-from-i64.c | 2 +- .../riscv/rvv/autovec/avg_ceil-run-1-i8-from-i16.c | 2 +- .../riscv/rvv/autovec/avg_ceil-run-1-i8-from-i32.c | 2 +- .../riscv/rvv/autovec/avg_ceil-run-1-i8-from-i64.c | 2 +- .../gcc.target/riscv/rvv/autovec/avg_data.h | 2 +- ...-i16-from-i32.c => avg_floor-1-i64-from-i128.c} | 4 +- .../rvv/autovec/avg_floor-run-1-i16-from-i32.c | 2 +- .../rvv/autovec/avg_floor-run-1-i16-from-i64.c | 2 +- .../rvv/autovec/avg_floor-run-1-i32-from-i64.c | 2 +- ...-from-i32.c => avg_floor-run-1-i64-from-i128.c} | 8 ++-- .../rvv/autovec/avg_floor-run-1-i8-from-i16.c | 2 +- .../rvv/autovec/avg_floor-run-1-i8-from-i32.c | 2 +- .../rvv/autovec/avg_floor-run-1-i8-from-i64.c | 2 +- .../gcc.target/riscv/sat/sat_s_add-1-i16.c | 27 +----------- .../gcc.target/riscv/sat/sat_s_add-1-i32.c | 26 +---------- .../gcc.target/riscv/sat/sat_s_add-1-i64.c | 24 +--------- .../gcc.target/riscv/sat/sat_s_add-1-i8.c | 25 +---------- .../gcc.target/riscv/sat/sat_s_add-2-i16.c | 27 +----------- .../gcc.target/riscv/sat/sat_s_add-2-i32.c | 26 +---------- .../gcc.target/riscv/sat/sat_s_add-2-i64.c | 24 +--------- .../gcc.target/riscv/sat/sat_s_add-2-i8.c | 25 +---------- .../gcc.target/riscv/sat/sat_s_add-3-i16.c | 27 +----------- .../gcc.target/riscv/sat/sat_s_add-3-i32.c | 26 +---------- .../gcc.target/riscv/sat/sat_s_add-3-i64.c | 24 +--------- .../gcc.target/riscv/sat/sat_s_add-3-i8.c | 25 +---------- .../gcc.target/riscv/sat/sat_s_add-4-i16.c | 27 +----------- .../gcc.target/riscv/sat/sat_s_add-4-i32.c | 26 +---------- .../gcc.target/riscv/sat/sat_s_add-4-i64.c | 24 +--------- .../gcc.target/riscv/sat/sat_s_add-4-i8.c | 25 +---------- .../gcc.target/riscv/sat/sat_s_add_imm-1-i16.c | 51 +--------------------- .../gcc.target/riscv/sat/sat_s_add_imm-1-i32.c | 47 +------------------- .../gcc.target/riscv/sat/sat_s_add_imm-1-i64.c | 41 +---------------- .../gcc.target/riscv/sat/sat_s_add_imm-1-i8.c | 42 +----------------- .../gcc.target/riscv/sat/sat_s_add_imm-2-i16.c | 50 +-------------------- .../gcc.target/riscv/sat/sat_s_add_imm-2-i32.c | 47 +------------------- .../gcc.target/riscv/sat/sat_s_add_imm-2-i64.c | 41 +---------------- .../gcc.target/riscv/sat/sat_s_add_imm-2-i8.c | 42 +----------------- .../gcc.target/riscv/sat/sat_s_sub-1-i16.c | 25 +---------- .../gcc.target/riscv/sat/sat_s_sub-1-i32.c | 23 +--------- .../gcc.target/riscv/sat/sat_s_sub-1-i64.c | 22 +--------- .../gcc.target/riscv/sat/sat_s_sub-1-i8.c | 23 +--------- .../gcc.target/riscv/sat/sat_s_sub-2-i16.c | 25 +---------- .../gcc.target/riscv/sat/sat_s_sub-2-i32.c | 23 +--------- .../gcc.target/riscv/sat/sat_s_sub-2-i64.c | 22 +--------- .../gcc.target/riscv/sat/sat_s_sub-2-i8.c | 23 +--------- .../gcc.target/riscv/sat/sat_s_sub-3-i16.c | 25 +---------- .../gcc.target/riscv/sat/sat_s_sub-3-i32.c | 23 +--------- .../gcc.target/riscv/sat/sat_s_sub-3-i64.c | 22 +--------- .../gcc.target/riscv/sat/sat_s_sub-3-i8.c | 23 +--------- .../gcc.target/riscv/sat/sat_s_sub-4-i16.c | 25 +---------- .../gcc.target/riscv/sat/sat_s_sub-4-i32.c | 23 +--------- .../gcc.target/riscv/sat/sat_s_sub-4-i64.c | 22 +--------- .../gcc.target/riscv/sat/sat_s_sub-4-i8.c | 23 +--------- .../gcc.target/riscv/sat/sat_s_trunc-1-i16-to-i8.c | 21 +-------- .../riscv/sat/sat_s_trunc-1-i32-to-i16.c | 23 +--------- .../gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i8.c | 21 +-------- .../riscv/sat/sat_s_trunc-1-i64-to-i16.c | 23 +--------- .../riscv/sat/sat_s_trunc-1-i64-to-i32.c | 21 +-------- .../gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i8.c | 21 +-------- .../gcc.target/riscv/sat/sat_s_trunc-2-i16-to-i8.c | 21 +-------- .../riscv/sat/sat_s_trunc-2-i32-to-i16.c | 23 +--------- .../gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i8.c | 21 +-------- .../riscv/sat/sat_s_trunc-2-i64-to-i16.c | 23 +--------- .../riscv/sat/sat_s_trunc-2-i64-to-i32.c | 21 +-------- .../gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i8.c | 21 +-------- .../gcc.target/riscv/sat/sat_s_trunc-3-i16-to-i8.c | 21 +-------- .../riscv/sat/sat_s_trunc-3-i32-to-i16.c | 23 +--------- .../gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i8.c | 21 +-------- .../riscv/sat/sat_s_trunc-3-i64-to-i16.c | 23 +--------- .../riscv/sat/sat_s_trunc-3-i64-to-i32.c | 21 +-------- .../gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i8.c | 21 +-------- .../gcc.target/riscv/sat/sat_s_trunc-4-i16-to-i8.c | 21 +-------- .../riscv/sat/sat_s_trunc-4-i32-to-i16.c | 23 +--------- .../gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i8.c | 21 +-------- .../riscv/sat/sat_s_trunc-4-i64-to-i16.c | 23 +--------- .../riscv/sat/sat_s_trunc-4-i64-to-i32.c | 21 +-------- .../gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i8.c | 21 +-------- .../gcc.target/riscv/sat/sat_s_trunc-5-i16-to-i8.c | 21 +-------- .../riscv/sat/sat_s_trunc-5-i32-to-i16.c | 23 +--------- .../gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i8.c | 21 +-------- .../riscv/sat/sat_s_trunc-5-i64-to-i16.c | 23 +--------- .../riscv/sat/sat_s_trunc-5-i64-to-i32.c | 21 +-------- .../gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i8.c | 21 +-------- .../gcc.target/riscv/sat/sat_s_trunc-6-i16-to-i8.c | 21 +-------- .../riscv/sat/sat_s_trunc-6-i32-to-i16.c | 23 +--------- .../gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i8.c | 21 +-------- .../riscv/sat/sat_s_trunc-6-i64-to-i16.c | 23 +--------- .../riscv/sat/sat_s_trunc-6-i64-to-i32.c | 21 +-------- .../gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i8.c | 21 +-------- .../gcc.target/riscv/sat/sat_s_trunc-7-i16-to-i8.c | 21 +-------- .../riscv/sat/sat_s_trunc-7-i32-to-i16.c | 23 +--------- .../gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i8.c | 21 +-------- .../riscv/sat/sat_s_trunc-7-i64-to-i16.c | 23 +--------- .../riscv/sat/sat_s_trunc-7-i64-to-i32.c | 21 +-------- .../gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i8.c | 21 +-------- .../gcc.target/riscv/sat/sat_s_trunc-8-i16-to-i8.c | 21 +-------- .../riscv/sat/sat_s_trunc-8-i32-to-i16.c | 23 +--------- .../gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i8.c | 21 +-------- .../riscv/sat/sat_s_trunc-8-i64-to-i16.c | 23 +--------- .../riscv/sat/sat_s_trunc-8-i64-to-i32.c | 21 +-------- .../gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i8.c | 21 +-------- .../gcc.target/riscv/sat/sat_u_add-1-u16.c | 16 +------ .../gcc.target/riscv/sat/sat_u_add-1-u32.c | 17 +------- .../gcc.target/riscv/sat/sat_u_add-1-u64.c | 12 +---- .../gcc.target/riscv/sat/sat_u_add-1-u8.c | 14 +----- .../gcc.target/riscv/sat/sat_u_add-2-u16.c | 16 +------ .../gcc.target/riscv/sat/sat_u_add-2-u32.c | 17 +------- .../gcc.target/riscv/sat/sat_u_add-2-u64.c | 12 +---- .../gcc.target/riscv/sat/sat_u_add-2-u8.c | 14 +----- .../gcc.target/riscv/sat/sat_u_add-3-u16.c | 16 +------ .../gcc.target/riscv/sat/sat_u_add-3-u32.c | 17 +------- .../gcc.target/riscv/sat/sat_u_add-3-u64.c | 12 +---- .../gcc.target/riscv/sat/sat_u_add-3-u8.c | 14 +----- .../gcc.target/riscv/sat/sat_u_add-4-u16.c | 16 +------ .../gcc.target/riscv/sat/sat_u_add-4-u32.c | 17 +------- .../gcc.target/riscv/sat/sat_u_add-4-u64.c | 12 +---- .../gcc.target/riscv/sat/sat_u_add-4-u8.c | 14 +----- .../gcc.target/riscv/sat/sat_u_add-5-u16.c | 16 +------ .../gcc.target/riscv/sat/sat_u_add-5-u32.c | 17 +------- .../gcc.target/riscv/sat/sat_u_add-5-u64.c | 12 +---- .../gcc.target/riscv/sat/sat_u_add-5-u8.c | 14 +----- .../gcc.target/riscv/sat/sat_u_add-6-u16.c | 16 +------ .../gcc.target/riscv/sat/sat_u_add-6-u32.c | 17 +------- .../gcc.target/riscv/sat/sat_u_add-6-u64.c | 12 +---- .../gcc.target/riscv/sat/sat_u_add-6-u8.c | 14 +----- .../riscv/sat/sat_u_add-7-u16-from-u32.c | 16 +------ .../riscv/sat/sat_u_add-7-u16-from-u64.c | 16 +------ .../riscv/sat/sat_u_add-7-u32-from-u64.c | 17 +------- .../gcc.target/riscv/sat/sat_u_add-7-u8-from-u16.c | 14 +----- .../gcc.target/riscv/sat/sat_u_add-7-u8-from-u32.c | 14 +----- .../gcc.target/riscv/sat/sat_u_add-7-u8-from-u64.c | 14 +----- .../gcc.target/riscv/sat/sat_u_add_imm-1-u16.c | 16 +------ .../gcc.target/riscv/sat/sat_u_add_imm-1-u32.c | 17 +------- .../gcc.target/riscv/sat/sat_u_add_imm-1-u64.c | 12 +---- .../gcc.target/riscv/sat/sat_u_add_imm-1-u8.c | 14 +----- .../gcc.target/riscv/sat/sat_u_add_imm-2-u16.c | 16 +------ .../gcc.target/riscv/sat/sat_u_add_imm-2-u32.c | 17 +------- .../gcc.target/riscv/sat/sat_u_add_imm-2-u64.c | 12 +---- .../gcc.target/riscv/sat/sat_u_add_imm-2-u8.c | 14 +----- .../gcc.target/riscv/sat/sat_u_add_imm-3-u16.c | 16 +------ .../gcc.target/riscv/sat/sat_u_add_imm-3-u32.c | 17 +------- .../gcc.target/riscv/sat/sat_u_add_imm-3-u64.c | 12 +---- .../gcc.target/riscv/sat/sat_u_add_imm-3-u8.c | 14 +----- .../gcc.target/riscv/sat/sat_u_add_imm-4-u16.c | 16 +------ .../gcc.target/riscv/sat/sat_u_add_imm-4-u32.c | 17 +------- .../gcc.target/riscv/sat/sat_u_add_imm-4-u64.c | 12 +---- .../gcc.target/riscv/sat/sat_u_add_imm-4-u8.c | 14 +----- .../riscv/sat/sat_u_mul-1-u16-from-u128.c | 1 + .../riscv/sat/sat_u_mul-1-u32-from-u128.c | 1 + .../riscv/sat/sat_u_mul-1-u64-from-u128.c | 1 + .../riscv/sat/sat_u_mul-1-u8-from-u128.c | 1 + .../gcc.target/riscv/sat/sat_u_sub-1-u16.c | 14 +----- .../gcc.target/riscv/sat/sat_u_sub-1-u32.c | 17 +------- .../gcc.target/riscv/sat/sat_u_sub-1-u64.c | 12 +---- .../gcc.target/riscv/sat/sat_u_sub-1-u8.c | 13 +----- .../gcc.target/riscv/sat/sat_u_sub-10-u16.c | 14 +----- .../gcc.target/riscv/sat/sat_u_sub-10-u32.c | 17 +------- .../gcc.target/riscv/sat/sat_u_sub-10-u64.c | 12 +---- .../gcc.target/riscv/sat/sat_u_sub-10-u8.c | 13 +----- .../gcc.target/riscv/sat/sat_u_sub-11-u16.c | 14 +----- .../gcc.target/riscv/sat/sat_u_sub-11-u32.c | 17 +------- .../gcc.target/riscv/sat/sat_u_sub-11-u64.c | 12 +---- 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.../gcc.target/riscv/sat/sat_u_sub_imm-1-u8-3.c | 14 +----- .../gcc.target/riscv/sat/sat_u_sub_imm-1-u8-4.c | 14 +----- .../gcc.target/riscv/sat/sat_u_sub_imm-1-u8.c | 14 +----- .../gcc.target/riscv/sat/sat_u_sub_imm-2-u16-1.c | 15 +------ .../gcc.target/riscv/sat/sat_u_sub_imm-2-u16-2.c | 16 +------ .../gcc.target/riscv/sat/sat_u_sub_imm-2-u16-3.c | 12 +---- .../gcc.target/riscv/sat/sat_u_sub_imm-2-u16.c | 14 +----- .../gcc.target/riscv/sat/sat_u_sub_imm-2-u32-1.c | 17 +------- .../gcc.target/riscv/sat/sat_u_sub_imm-2-u32-2.c | 18 +------- .../gcc.target/riscv/sat/sat_u_sub_imm-2-u32-3.c | 10 +---- .../gcc.target/riscv/sat/sat_u_sub_imm-2-u32.c | 15 +------ .../gcc.target/riscv/sat/sat_u_sub_imm-2-u64-1.c | 10 +---- .../gcc.target/riscv/sat/sat_u_sub_imm-2-u64.c | 12 +---- .../gcc.target/riscv/sat/sat_u_sub_imm-2-u8-1.c | 13 +----- .../gcc.target/riscv/sat/sat_u_sub_imm-2-u8-2.c | 13 +----- .../gcc.target/riscv/sat/sat_u_sub_imm-2-u8-3.c | 11 +---- .../gcc.target/riscv/sat/sat_u_sub_imm-2-u8.c | 13 +----- .../gcc.target/riscv/sat/sat_u_sub_imm-3-u16-1.c | 16 +------ .../gcc.target/riscv/sat/sat_u_sub_imm-3-u16-2.c | 16 +------ .../gcc.target/riscv/sat/sat_u_sub_imm-3-u16.c | 15 +------ .../gcc.target/riscv/sat/sat_u_sub_imm-3-u32-1.c | 18 +------- .../gcc.target/riscv/sat/sat_u_sub_imm-3-u32-2.c | 18 +------- .../gcc.target/riscv/sat/sat_u_sub_imm-3-u32.c | 16 +------ .../gcc.target/riscv/sat/sat_u_sub_imm-3-u64.c | 13 +----- .../gcc.target/riscv/sat/sat_u_sub_imm-3-u8-1.c | 14 +----- .../gcc.target/riscv/sat/sat_u_sub_imm-3-u8-2.c | 14 +----- .../gcc.target/riscv/sat/sat_u_sub_imm-3-u8.c | 14 +----- .../gcc.target/riscv/sat/sat_u_sub_imm-4-u16-1.c | 15 +------ .../gcc.target/riscv/sat/sat_u_sub_imm-4-u16-2.c | 16 +------ .../gcc.target/riscv/sat/sat_u_sub_imm-4-u16.c | 14 +----- .../gcc.target/riscv/sat/sat_u_sub_imm-4-u32-1.c | 17 +------- .../gcc.target/riscv/sat/sat_u_sub_imm-4-u32-2.c | 18 +------- .../gcc.target/riscv/sat/sat_u_sub_imm-4-u32.c | 15 +------ .../gcc.target/riscv/sat/sat_u_sub_imm-4-u64.c | 12 +---- .../gcc.target/riscv/sat/sat_u_sub_imm-4-u8-1.c | 13 +----- .../gcc.target/riscv/sat/sat_u_sub_imm-4-u8-2.c | 13 +----- .../gcc.target/riscv/sat/sat_u_sub_imm-4-u8.c | 13 +----- .../gcc.target/riscv/sat/sat_u_trunc-1-u16.c | 15 +------ .../gcc.target/riscv/sat/sat_u_trunc-1-u32.c | 14 +----- .../gcc.target/riscv/sat/sat_u_trunc-1-u64.c | 12 +---- .../gcc.target/riscv/sat/sat_u_trunc-1-u8.c | 12 +---- .../gcc.target/riscv/sat/sat_u_trunc-2-u16.c | 15 +------ .../gcc.target/riscv/sat/sat_u_trunc-2-u32.c | 12 +---- .../gcc.target/riscv/sat/sat_u_trunc-2-u64.c | 15 +------ .../gcc.target/riscv/sat/sat_u_trunc-2-u8.c | 12 +---- .../gcc.target/riscv/sat/sat_u_trunc-3-u16.c | 12 +---- .../gcc.target/riscv/sat/sat_u_trunc-3-u32.c | 12 +---- .../gcc.target/riscv/sat/sat_u_trunc-3-u64.c | 15 +------ .../gcc.target/riscv/sat/sat_u_trunc-3-u8.c | 14 +----- .../gcc.target/riscv/sat/sat_u_trunc-4-u16.c | 15 +------ .../gcc.target/riscv/sat/sat_u_trunc-4-u32.c | 14 +----- .../gcc.target/riscv/sat/sat_u_trunc-4-u64.c | 12 +---- .../gcc.target/riscv/sat/sat_u_trunc-4-u8.c | 12 +---- .../gcc.target/riscv/sat/sat_u_trunc-5-u16.c | 15 +------ .../gcc.target/riscv/sat/sat_u_trunc-5-u32.c | 12 +---- .../gcc.target/riscv/sat/sat_u_trunc-5-u64.c | 15 +------ .../gcc.target/riscv/sat/sat_u_trunc-5-u8.c | 12 +---- .../gcc.target/riscv/sat/sat_u_trunc-6-u16.c | 12 +---- .../gcc.target/riscv/sat/sat_u_trunc-6-u32.c | 12 +---- .../gcc.target/riscv/sat/sat_u_trunc-6-u64.c | 15 +------ .../gcc.target/riscv/sat/sat_u_trunc-6-u8.c | 14 +----- 279 files changed, 554 insertions(+), 4120 deletions(-) copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{avg_floor-1-i16-from-i32.c => avg [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{avg_floor-run-1-i16-from-i32.c => [...] -- To stop receiving notification emails like this one, please contact the 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[binutils-gdb] branch binutils-2_45-branch updated (153c98d1d5f -> 9d44d46d993)

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[binutils-gdb] branch gdb-16-branch updated (3eb81ecd26f -> 11e4b92b66e)

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[binutils-gdb] branch binutils-2_44-branch updated (8e98f97aecb -> 76ce75b5239)

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