Tcwg-commits April 2025

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[gcc] branch releases/gcc-14 updated (4d5fd1176d1 -> 6a66212916e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch releases/gcc-14 in repository gcc. from 4d5fd1176d1 LoongArch: Fix awk / sed usage for compatibility new 47b509fef53 [RISC-V][PR target/116256] Fix incorrect return value for p [...] new f3ac41f8424 [RISC-V][PR target/116308] Fix generation of initial RTL fo [...] new e4586ae3184 [PR target/118357] RISC-V: Disable fusing vsetvl instructio [...] new af3ebb414e2 RISC-V: Move fortran testcase to gfortran.target new 1eb6bf31283 RISC-V: Fix code gen for reduction with length 0 [PR118182] new 6f549f865d0 RISC-V: Fix vsetvl compatibility predicate [PR118154]. new 08e381e8af3 RISC-V: Disallow negative step for interleaving [PR117682] new 46732eb89db [PATCH] riscv: add mising masking in lrsc expander (PR118137) new 6547906bdbd [RISC-V][PR target/106544] Avoid ICEs due to bogus asms new ca6adeda373 RISC-V: Fix compress shuffle pattern [PR117383]. new acb636a9c3a RISC-V: Add assert for insn operand out of range access [PR [...] new 164aededa82 RISC-V: Ensure vtype for full-register moves [PR117544]. new 37d13153635 [PATCH v3] RISC-V: Fixed incorrect semantic description in [...] new 80ab2514256 [PATCH 1/2] RISC-V: Fix the outer_code when calculating the [...] new 5b3558944a7 [PATCH] RISC-V: Fix th.extu operands exceeding range on rv32. new d0663c14307 [PATCH] RISC-V: Allow zero operand for DI variants of vssubu.vx new 5615fea2fce riscv: Fix duplicate assmbler label in @tlsdesc<mode> insn new 94b774c5c1c RISC-V: Fix vl_used_by_non_rvv_insn logic of vsetvl pass new 4f41d8fa5a7 [PATCH v4] [target/116592] RISC-V: Fix illegal operands "th [...] new e19a21f8edd RISC-V: Fix subreg of VLS modes larger than a vector [PR116086]. new d2f5d28415f RISC-V: Add missing mode_idx for vrol and vror new 327c7c38123 RISC-V: Fix factor in dwarf_poly_indeterminate_value [PR116305] new 28fe2b087ba RISC-V: Delete duplicate '#define RISCV_DWARF_VLENB' new 86b0f63adb0 [RISC-V][PR target/116240] Ensure object is a comparison be [...] new 95ac2d8afb3 RISC-V: Correct mode_idx attribute for viwalu wx variants [ [...] new eaf423763c7 RISC-V: Reject 'd' extension with ILP32E ABI new b7d97594502 RISC-V: Error early with V and no M extension. new cdb987e977e [committed] [RISC-V] Fix false-positive uninitialized variable new 6cd78e383a9 RISC-V: Bugfix for max_sew_overlap_and_next_ratio_valid_for [...] new 4bd63c709de RISC-V:Bugfix for vlmul_ext and vlmul_trunc with NULL retur [...] new 6a66212916e RISC-V: Fix vid const vector expander for non-npatterns size steps The 31 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/riscv/autovec-opt.md | 10 +- gcc/config/riscv/autovec.md | 86 ++++++- gcc/config/riscv/predicates.md | 8 +- gcc/config/riscv/riscv-protos.h | 6 +- gcc/config/riscv/riscv-v.cc | 93 +++++++- gcc/config/riscv/riscv-vector-builtins-bases.cc | 4 + gcc/config/riscv/riscv-vsetvl.cc | 44 +++- gcc/config/riscv/riscv-vsetvl.def | 4 +- gcc/config/riscv/riscv.cc | 194 ++++++++++----- gcc/config/riscv/riscv.h | 2 - gcc/config/riscv/riscv.md | 31 +-- gcc/config/riscv/sync.md | 1 + gcc/config/riscv/thead.cc | 4 +- gcc/config/riscv/thead.md | 4 +- gcc/config/riscv/vector-iterators.md | 261 +++++++++++++++++++++ gcc/config/riscv/vector.md | 236 +++++++++++++++++-- gcc/testsuite/gcc.dg/atomic/pr118137.c | 29 +++ gcc/testsuite/gcc.target/riscv/arch-31.c | 2 +- gcc/testsuite/gcc.target/riscv/arch-32.c | 2 +- gcc/testsuite/gcc.target/riscv/arch-41.c | 7 + gcc/testsuite/gcc.target/riscv/compare-debug-1.c | 2 +- gcc/testsuite/gcc.target/riscv/compare-debug-2.c | 2 +- gcc/testsuite/gcc.target/riscv/pr106544.c | 6 + gcc/testsuite/gcc.target/riscv/pr116111.c | 7 + gcc/testsuite/gcc.target/riscv/pr116240.c | 12 + gcc/testsuite/gcc.target/riscv/pr116308.c | 9 + gcc/testsuite/gcc.target/riscv/pr117483.c | 20 ++ gcc/testsuite/gcc.target/riscv/predef-14.c | 6 +- gcc/testsuite/gcc.target/riscv/predef-15.c | 4 +- gcc/testsuite/gcc.target/riscv/predef-16.c | 4 +- gcc/testsuite/gcc.target/riscv/predef-26.c | 6 +- gcc/testsuite/gcc.target/riscv/predef-27.c | 6 +- gcc/testsuite/gcc.target/riscv/predef-32.c | 6 +- gcc/testsuite/gcc.target/riscv/predef-33.c | 6 +- .../riscv/rvv/autovec/binop/vcompress-avlprop-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/pr111486.c | 2 +- .../gcc.target/riscv/rvv/autovec/pr116086-2-run.c | 6 + .../gcc.target/riscv/rvv/autovec/pr116086-2.c | 18 ++ .../gcc.target/riscv/rvv/autovec/pr116086.c | 76 ++++++ .../gcc.target/riscv/rvv/autovec/pr116149.c | 18 ++ .../gcc.target/riscv/rvv/autovec/pr117383.c | 48 ++++ .../gcc.target/riscv/rvv/autovec/pr117682.c | 15 ++ .../gcc.target/riscv/rvv/autovec/pr118154-1.c | 23 ++ .../gcc.target/riscv/rvv/autovec/pr118154-2.c | 31 +++ .../gcc.target/riscv/rvv/autovec/pr118182-1.c | 28 +++ .../gcc.target/riscv/rvv/autovec/pr118182-2.c | 27 +++ gcc/testsuite/gcc.target/riscv/rvv/autovec/rotr.c | 13 + .../gcc.target/riscv/rvv/base/abi-call-args-4.c | 1 + gcc/testsuite/gcc.target/riscv/rvv/base/pr116036.c | 11 + gcc/testsuite/gcc.target/riscv/rvv/base/pr117286.c | 16 ++ gcc/testsuite/gcc.target/riscv/rvv/base/pr117544.c | 14 ++ .../riscv/rvv/base/scalable_vector_cfi.c | 32 +++ gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-1.c | 11 + gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-2.c | 11 + .../gcc.target/riscv/rvv/vsetvl/vsetvl_bug-3.c | 17 ++ .../gcc.target/riscv/rvv/xtheadvector/pr116592.c | 38 +++ .../gcc.target/riscv/rvv/xtheadvector/pr118357.c | 13 + gcc/testsuite/gcc.target/riscv/xtheadbb-extu-4.c | 17 ++ .../gcc.target/riscv/zfa-fmovh-fmovp-bug.c | 9 + .../riscv/rvv}/pr111395.f90 | 0 .../riscv/rvv}/pr111566.f90 | 0 gcc/testsuite/gfortran.target/riscv/rvv/pr118182.f | 63 +++++ .../riscv/rvv/rvv.exp} | 2 +- gcc/testsuite/lib/target-supports.exp | 37 +++ 64 files changed, 1557 insertions(+), 166 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/atomic/pr118137.c create mode 100644 gcc/testsuite/gcc.target/riscv/arch-41.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr106544.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr116111.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr116240.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr116308.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr117483.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr116086-2-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr116086-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr116086.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr116149.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117383.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117682.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr118154-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr118154-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr118182-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr118182-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/rotr.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr116036.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr117286.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr117544.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/scalable_vector_cfi.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116592.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr118357.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp-bug.c rename gcc/testsuite/{gcc.target/riscv/rvv/fortran => gfortran.target/riscv/rvv}/p [...] rename gcc/testsuite/{gcc.target/riscv/rvv/fortran => gfortran.target/riscv/rvv}/p [...] create mode 100644 gcc/testsuite/gfortran.target/riscv/rvv/pr118182.f rename gcc/testsuite/{gcc.target/riscv/rvv/rvv-fortran.exp => gfortran.target/risc [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 weeks, 4 days

[binutils-gdb] branch master updated (92d4a12d9e9 -> 0ab7a3242d3)

by git＠git.linaro.org

2 weeks, 4 days

[gcc] branch master updated (0f74d1e38a7 -> 9ea6bdac02a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 0f74d1e38a7 [committed][RISC-V] Adjust expected output for rvv test new 9ea6bdac02a deref-before-check-pr113253.c: Fix bogus warnings on lp32 The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/testsuite/gcc.dg/analyzer/deref-before-check-pr113253.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 weeks, 4 days

[gcc] branch master updated (39deb26060e -> 0f74d1e38a7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 39deb26060e riscv: Fix r15-9270 fallout on RISC-V new 0f74d1e38a7 [committed][RISC-V] Adjust expected output for rvv test The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117722.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 weeks, 4 days

[gcc] branch master updated (088887de771 -> 39deb26060e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 088887de771 rtl-optimization/119689 - compare-debug failure with LRA new 39deb26060e riscv: Fix r15-9270 fallout on RISC-V The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/riscv/riscv-vector-builtins.cc | 34 ++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 weeks, 4 days

[gcc] branch master updated (3e3b665cc77 -> 088887de771)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 3e3b665cc77 d: Use CONSTRUCTOR_ZERO_PADDING_BITS in the D FE [PR117832] new 088887de771 rtl-optimization/119689 - compare-debug failure with LRA The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/lra-remat.cc | 2 +- gcc/testsuite/g++.target/i386/pr119689.C | 44 ++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/g++.target/i386/pr119689.C -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 weeks, 4 days

[gcc] branch master updated (24d1832e0d6 -> 3e3b665cc77)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 24d1832e0d6 Revert "RISC-V: Refine the testcases for cond_widen_complicate-3" new 3e3b665cc77 d: Use CONSTRUCTOR_ZERO_PADDING_BITS in the D FE [PR117832] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/d/d-codegen.cc | 32 +++++++++++++++++++++++--------- gcc/d/d-convert.cc | 4 ++-- gcc/d/d-tree.h | 1 + gcc/d/decl.cc | 2 +- gcc/d/expr.cc | 22 ++++++++++++---------- gcc/d/modules.cc | 4 ++-- gcc/d/typeinfo.cc | 8 ++++---- 7 files changed, 45 insertions(+), 28 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 weeks, 4 days

[gcc] branch master updated (6e77a83ffbe -> 24d1832e0d6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 6e77a83ffbe libcpp: Fix error recovery after use of __VA_ARGS__ as macr [...] new 24d1832e0d6 Revert "RISC-V: Refine the testcases for cond_widen_complicate-3" The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../rvv/autovec/cond/cond_widen_complicate-3-f16.c | 9 --------- .../rvv/autovec/cond/cond_widen_complicate-3-f32.c | 9 --------- .../rvv/autovec/cond/cond_widen_complicate-3-i16.c | 9 --------- .../rvv/autovec/cond/cond_widen_complicate-3-i32.c | 9 --------- .../rvv/autovec/cond/cond_widen_complicate-3-i8.c | 9 --------- .../rvv/autovec/cond/cond_widen_complicate-3-u16.c | 9 --------- .../rvv/autovec/cond/cond_widen_complicate-3-u32.c | 9 --------- .../rvv/autovec/cond/cond_widen_complicate-3-u8.c | 9 --------- .../cond_widen_complicate-3.c} | 13 +++++++------ .../rvv/autovec/cond/cond_widen_complicate-3.h | 21 --------------------- 10 files changed, 7 insertions(+), 99 deletions(-) delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_comp [...] delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_comp [...] delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_comp [...] delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_comp [...] delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_comp [...] delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_comp [...] delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_comp [...] delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_comp [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{widen/widen-complicate-3.c => con [...] delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_comp [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 weeks, 5 days

[gcc] branch master updated (f183ae0ae89 -> 6e77a83ffbe)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from f183ae0ae89 expr: Use constant_lower_bound classifying constructor els [...] new ac1044da4b3 testsuite: Add -mabi to pr116595.C new 6e77a83ffbe libcpp: Fix error recovery after use of __VA_ARGS__ as macr [...] The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/testsuite/g++.target/riscv/rvv/autovec/pr116595.C | 2 +- gcc/testsuite/gcc.dg/cpp/pr118674.c | 5 +++++ libcpp/macro.cc | 7 ++++--- 3 files changed, 10 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/cpp/pr118674.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 weeks, 5 days

[binutils-gdb] branch master updated (981fe5fd80f -> 92d4a12d9e9)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from 981fe5fd80f s390: Add support for z17 as CPU name new 1bafda2c459 [gdb/symtab] Handle DW_OP_entry_value at function entry new 92d4a12d9e9 [gdb/testsuite] Allow thread exited message in gdb.threads/ [...] The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gdb/dwarf2/expr.c | 88 ++++++++++++--- gdb/dwarf2/expr.h | 4 + .../dw2-entry-value-2.c} | 15 +-- gdb/testsuite/gdb.dwarf2/dw2-entry-value-2.exp | 125 +++++++++++++++++++++ .../gdb.threads/infcall-from-bp-cond-simple.exp | 8 +- gdb/testsuite/lib/dwarf.exp | 23 +++- 6 files changed, 236 insertions(+), 27 deletions(-) copy gdb/testsuite/{gdb.python/py-commands-breakpoint.c => gdb.dwarf2/dw2-entry-va [...] create mode 100644 gdb/testsuite/gdb.dwarf2/dw2-entry-value-2.exp -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 weeks, 5 days

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Tcwg-commits April 2025