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from abfc1405796 Adjust v850 rotate expander to allow more cases for V850E3V5
new efcfd1d2ad8 t-rtems: add rv32imf architecture to the RTEMS multilib for RISC-V
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gcc/config/riscv/t-rtems | 5 +++--
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new baeb0a958cf Update release readme after making 2.43.1 release
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binutils/README-how-to-make-a-release | 60 +++++++++++++++++++++++------------
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unknown user pushed a change to branch binutils-2_43-branch
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bfd/development.sh | 2 +-
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unknown user pushed a change to annotated tag binutils-2_43_1
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tagging beb2cdbcda911764b2bed5e57921fe90493260bd (commit)
replaces binutils-2_43
tagged by Nick Clifton
on Sat Aug 17 17:55:32 2024 +0100
- Log -----------------------------------------------------------------
Official GNU Binutils 2.43.1 release
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This annotated tag includes the following new commits:
new beb2cdbcda9 This is the 2.43.1 release
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unknown user pushed a change to branch binutils-2_43-branch
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new beb2cdbcda9 This is the 2.43.1 release
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Summary of changes:
ChangeLog.git | 295 ++++++++++++++++++++++++++++++++++++-
bfd/configure | 20 +--
bfd/development.sh | 2 +-
bfd/po/bfd.pot | 344 +++++++++++++++++++++----------------------
bfd/version.m4 | 2 +-
binutils/configure | 20 +--
gas/configure | 20 +--
gas/po/gas.pot | 386 ++++++++++++++++++++++++-------------------------
gprof/configure | 20 +--
ld/configure | 20 +--
ld/po/ld.pot | 22 +--
opcodes/configure | 20 +--
opcodes/po/opcodes.pot | 2 +-
13 files changed, 726 insertions(+), 447 deletions(-)
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unknown user pushed a change to branch master
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from 6d734ba4855 RISC-V: Fix ICE for vector single-width integer multiply-ad [...]
new abfc1405796 Adjust v850 rotate expander to allow more cases for V850E3V5
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gcc/config/v850/v850.md | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
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from 3f51684ac05 RISC-V: Bugfix for RVV rounding intrinsic ICE in function checker
new 7aed8dedeb9 [RISC-V][PR target/116282] Stabilize pattern conditions
new 6d734ba4855 RISC-V: Fix ICE for vector single-width integer multiply-ad [...]
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Summary of changes:
gcc/config/riscv/bitmanip.md | 2 +-
gcc/config/riscv/riscv-protos.h | 2 +-
gcc/config/riscv/riscv.cc | 66 +++++++++++++-------
gcc/config/riscv/riscv.md | 16 ++---
gcc/config/riscv/vector.md | 80 ++++++++++++-------------
gcc/testsuite/gcc.target/riscv/pr116282.c | 16 +++++
gcc/testsuite/gcc.target/riscv/rvv/base/bug-7.c | 26 ++++++++
gcc/testsuite/gcc.target/riscv/rvv/base/bug-8.c | 26 ++++++++
8 files changed, 163 insertions(+), 71 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/pr116282.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-8.c
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from 06ae7bc1345 RISC-V: Bugfix incorrect operand for vwsll auto-vect
new 3f51684ac05 RISC-V: Bugfix for RVV rounding intrinsic ICE in function checker
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gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-vector-builtins.cc | 4 ++--
gcc/config/riscv/riscv.cc | 5 ++++-
gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c | 13 +++++++++++++
4 files changed, 20 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c
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from 54b228d80c5 RISC-V: Add auto-vect pattern for vector rotate shift
new 06ae7bc1345 RISC-V: Bugfix incorrect operand for vwsll auto-vect
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gcc/config/riscv/autovec-opt.md | 4 ++++
gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-1.c | 14 ++++++++++++++
gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-2.c | 10 ++++++++++
3 files changed, 28 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-2.c
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