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unknown user pushed a change to branch releases/gcc-14
in repository gcc.
from cff270707f1 RISC-V: NO_WARNING preferred else value for RVV
new 21c8708ba63 libstdc++: Fix std::to_array for trivial-ish types [PR115522]
new d920658cbb2 libstdc++: Fix unwanted #pragma messages from PSTL headers [...]
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Summary of changes:
libstdc++-v3/include/pstl/pstl_config.h | 2 +-
libstdc++-v3/include/std/array | 8 ++++--
.../23_containers/array/creation/115522.cc | 33 ++++++++++++++++++++++
3 files changed, 40 insertions(+), 3 deletions(-)
create mode 100644 libstdc++-v3/testsuite/23_containers/array/creation/115522.cc
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unknown user pushed a change to branch releases/gcc-11
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from 3916b8853ff Daily bump.
new 30ffca55041 libstdc++: Add missing exports for ppc64le --with-long-doub [...]
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.../post/powerpc64-linux-gnu/baseline_symbols.txt | 12 ++++++++
.../src/c++11/compatibility-ldbl-alt128.cc | 36 ++++++++++++++++++++++
2 files changed, 48 insertions(+)
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unknown user pushed a change to branch releases/gcc-14
in repository gcc.
from 29b2e1cdb6f Fortran: Fix ICEs due to comp calls in initialization exprs [...]
new cff270707f1 RISC-V: NO_WARNING preferred else value for RVV
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Summary of changes:
gcc/config/riscv/riscv.cc | 6 +++++-
gcc/testsuite/gcc.dg/vect/pr115840.c | 11 +++++++++++
2 files changed, 16 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.dg/vect/pr115840.c
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unknown user pushed a change to branch master
in repository gcc.
from 26dfb3f2d30 [libstdc++] [testsuite] require dfprt on some tests
new 7bcef7532b1 aarch64: Avoid alloca in target attribute parsing
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gcc/config/aarch64/aarch64.cc | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
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unknown user pushed a change to branch master
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from c6f38e5e6d9 RISC-V: NO_WARNING preferred else value for RVV
new ccfe7151803 [alpha] adjust MEM alignment for block move [PR115459]
new 26dfb3f2d30 [libstdc++] [testsuite] require dfprt on some tests
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Summary of changes:
gcc/config/alpha/alpha.cc | 12 ++++++++++++
libstdc++-v3/testsuite/decimal/binary-arith.cc | 2 +-
libstdc++-v3/testsuite/decimal/comparison.cc | 2 +-
.../testsuite/decimal/compound-assignment-memfunc.cc | 2 +-
libstdc++-v3/testsuite/decimal/compound-assignment.cc | 2 +-
libstdc++-v3/testsuite/decimal/make-decimal.cc | 2 +-
libstdc++-v3/testsuite/decimal/pr54036-1.cc | 2 +-
libstdc++-v3/testsuite/decimal/pr54036-2.cc | 2 +-
libstdc++-v3/testsuite/decimal/pr54036-3.cc | 2 +-
libstdc++-v3/testsuite/decimal/unary-arith.cc | 2 +-
10 files changed, 21 insertions(+), 9 deletions(-)
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unknown user pushed a change to branch master
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from a55d24b3cf7 fortran: Factor the evaluation of MINLOC/MAXLOC's BACK argument
new c6f38e5e6d9 RISC-V: NO_WARNING preferred else value for RVV
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Summary of changes:
gcc/config/riscv/riscv.cc | 6 +++++-
gcc/testsuite/gcc.dg/vect/pr115840.c | 11 +++++++++++
2 files changed, 16 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.dg/vect/pr115840.c
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unknown user pushed a change to branch master
in repository gcc.
from 63d7d5998e3 RISC-V: Disable misaligned vector access in hook riscv_slow [...]
new a55d24b3cf7 fortran: Factor the evaluation of MINLOC/MAXLOC's BACK argument
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Summary of changes:
gcc/fortran/trans-intrinsic.cc | 10 ++
gcc/testsuite/gfortran.dg/maxloc_5.f90 | 257 +++++++++++++++++++++++++++++++++
gcc/testsuite/gfortran.dg/minloc_5.f90 | 257 +++++++++++++++++++++++++++++++++
3 files changed, 524 insertions(+)
create mode 100644 gcc/testsuite/gfortran.dg/maxloc_5.f90
create mode 100644 gcc/testsuite/gfortran.dg/minloc_5.f90
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unknown user pushed a change to branch master
in repository gcc.
from 3ea47ea1fca RISC-V: Add SiFive extensions, xsfvcp and xsfcease
new 63d7d5998e3 RISC-V: Disable misaligned vector access in hook riscv_slow [...]
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Summary of changes:
gcc/config/riscv/riscv.cc | 5 ++-
gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c | 52 ++++++++++++++++++++++
2 files changed, 55 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c
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unknown user pushed a change to branch master
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from f7e40003978 rs6000: Remove vcond{,u} expanders
new 3ea47ea1fca RISC-V: Add SiFive extensions, xsfvcp and xsfcease
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gcc/common/config/riscv/riscv-common.cc | 8 ++++++++
gcc/config/riscv/riscv.opt | 7 +++++++
gcc/testsuite/gcc.target/riscv/predef-sf-1.c | 19 +++++++++++++++++++
gcc/testsuite/gcc.target/riscv/predef-sf-2.c | 14 ++++++++++++++
4 files changed, 48 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/predef-sf-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/predef-sf-2.c
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tcwg-buildslave pushed a change to branch master
in repository toolchain/ci/interesting-commits.
from e4df67ac9 Add entry 29b8b72117845dc3d20e70fbfa85c590fa9c7830 from https [...]
new 929d2503b Add entry 29b8b72117845dc3d20e70fbfa85c590fa9c7830 from https [...]
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Summary of changes:
llvm/sha1/29b8b72117845dc3d20e70fbfa85c590fa9c7830/jira/description | 5 +++++
llvm/sha1/29b8b72117845dc3d20e70fbfa85c590fa9c7830/jira/yaml | 5 +++++
llvm/sha1/29b8b72117845dc3d20e70fbfa85c590fa9c7830/status.txt | 5 +++++
.../llvm-aarch64-master-Os_LTO/details.txt | 5 +++++
.../llvm-aarch64-master-Os_LTO/reproduction_instructions.txt | 4 ++--
.../llvm-aarch64-master-Os_LTO/status-summary.txt | 0
.../llvm-aarch64-master-Os_LTO/status.txt | 4 ++--
.../tcwg_bmk-code_speed-cpu2017rate}/status-summary.txt | 0
.../tcwg_bmk-code_speed-cpu2017rate/status.txt | 6 +++---
9 files changed, 27 insertions(+), 7 deletions(-)
create mode 100644 llvm/sha1/29b8b72117845dc3d20e70fbfa85c590fa9c7830/tcwg_bmk-cod [...]
copy llvm/sha1/29b8b72117845dc3d20e70fbfa85c590fa9c7830/{tcwg_bmk-code_size-spec2k [...]
copy llvm/sha1/{ae4f3001338c2a19167abf8dbe69d15f5209e033 => 29b8b72117845dc3d20e70 [...]
copy llvm/sha1/{ae4f3001338c2a19167abf8dbe69d15f5209e033 => 29b8b72117845dc3d20e70 [...]
copy llvm/sha1/{ae4f3001338c2a19167abf8dbe69d15f5209e033/tcwg_bmk-code_speed-cpu20 [...]
copy llvm/sha1/{e16f2f5d2491fde19afb63d5cec83625d391be30 => 29b8b72117845dc3d20e70 [...]
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