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from b55a35bcc80 libfortran: Fix handling of formatted separators.
new d80c9df20ed i386: Fix Sierra Forest auto dispatch
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Summary of changes:
gcc/common/config/i386/i386-common.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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unknown user pushed a change to branch master
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from b991193eb8a RISC-V: Add xfail test case for highpart overlap floating-p [...]
new 1b7785fdf95 s390x: Do not default to -mvx for -mesa
new 6b5248d15c6 i386: Fix Sierra Forest auto dispatch
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Summary of changes:
gcc/common/config/i386/i386-common.cc | 2 +-
gcc/config/s390/s390.cc | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
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unknown user pushed a change to branch master
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from 4df96b4ec78 Revert "RISC-V: Support highpart overlap for floating-point [...]
new b991193eb8a RISC-V: Add xfail test case for highpart overlap floating-p [...]
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Summary of changes:
.../gcc.target/riscv/rvv/base/pr112431-10.c | 104 ++++++++++++
.../gcc.target/riscv/rvv/base/pr112431-11.c | 68 ++++++++
.../gcc.target/riscv/rvv/base/pr112431-12.c | 51 ++++++
.../gcc.target/riscv/rvv/base/pr112431-13.c | 188 +++++++++++++++++++++
.../gcc.target/riscv/rvv/base/pr112431-14.c | 119 +++++++++++++
.../gcc.target/riscv/rvv/base/pr112431-15.c | 86 ++++++++++
.../riscv/rvv/base/{pr112431-25.c => pr112431-7.c} | 78 ++++-----
.../riscv/rvv/base/{pr112431-26.c => pr112431-8.c} | 44 ++---
.../riscv/rvv/base/{pr112431-27.c => pr112431-9.c} | 26 +--
9 files changed, 690 insertions(+), 74 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-13.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-14.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-15.c
copy gcc/testsuite/gcc.target/riscv/rvv/base/{pr112431-25.c => pr112431-7.c} (50%)
copy gcc/testsuite/gcc.target/riscv/rvv/base/{pr112431-26.c => pr112431-8.c} (56%)
copy gcc/testsuite/gcc.target/riscv/rvv/base/{pr112431-27.c => pr112431-9.c} (64%)
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unknown user pushed a change to branch master
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from a367b99f916 RISC-V: Add xfail test case for indexed load overlap with S [...]
new 4df96b4ec78 Revert "RISC-V: Support highpart overlap for floating-point [...]
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Summary of changes:
gcc/config/riscv/vector.md | 78 ++++-----
.../gcc.target/riscv/rvv/base/pr112431-10.c | 104 ------------
.../gcc.target/riscv/rvv/base/pr112431-11.c | 68 --------
.../gcc.target/riscv/rvv/base/pr112431-12.c | 51 ------
.../gcc.target/riscv/rvv/base/pr112431-13.c | 188 ---------------------
.../gcc.target/riscv/rvv/base/pr112431-14.c | 119 -------------
.../gcc.target/riscv/rvv/base/pr112431-15.c | 86 ----------
.../gcc.target/riscv/rvv/base/pr112431-7.c | 106 ------------
.../gcc.target/riscv/rvv/base/pr112431-8.c | 68 --------
.../gcc.target/riscv/rvv/base/pr112431-9.c | 51 ------
10 files changed, 37 insertions(+), 882 deletions(-)
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-10.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-11.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-12.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-13.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-14.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-15.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-7.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-8.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-9.c
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unknown user pushed a change to branch master
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from 9257c7a7205 Revert "RISC-V: Support highpart overlap for indexed load w [...]
new a367b99f916 RISC-V: Add xfail test case for indexed load overlap with S [...]
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Summary of changes:
.../rvv/base/{pr112431-34.c => pr112431-28.c} | 9 ++++--
.../riscv/rvv/base/{pr112431-2.c => pr112431-29.c} | 34 +++++++++++-----------
.../riscv/rvv/base/{pr112431-3.c => pr112431-30.c} | 18 ++++++------
.../rvv/base/{pr112431-16.c => pr112431-31.c} | 32 ++++++++++----------
.../rvv/base/{pr112431-17.c => pr112431-32.c} | 16 +++++-----
.../rvv/base/{pr112431-18.c => pr112431-33.c} | 16 +++++-----
.../gcc.target/riscv/rvv/base/pr112431-34.c | 2 +-
7 files changed, 65 insertions(+), 62 deletions(-)
copy gcc/testsuite/gcc.target/riscv/rvv/base/{pr112431-34.c => pr112431-28.c} (92%)
copy gcc/testsuite/gcc.target/riscv/rvv/base/{pr112431-2.c => pr112431-29.c} (56%)
copy gcc/testsuite/gcc.target/riscv/rvv/base/{pr112431-3.c => pr112431-30.c} (64%)
copy gcc/testsuite/gcc.target/riscv/rvv/base/{pr112431-16.c => pr112431-31.c} (59%)
copy gcc/testsuite/gcc.target/riscv/rvv/base/{pr112431-17.c => pr112431-32.c} (68%)
copy gcc/testsuite/gcc.target/riscv/rvv/base/{pr112431-18.c => pr112431-33.c} (68%)
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unknown user pushed a change to branch master
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from 16aea8c584e s390: testsuite: Remove xfail for vpopct{b,h}
new 9257c7a7205 Revert "RISC-V: Support highpart overlap for indexed load w [...]
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Summary of changes:
gcc/config/riscv/vector.md | 63 ++++++-------
.../gcc.target/riscv/rvv/base/pr112431-28.c | 104 ---------------------
.../gcc.target/riscv/rvv/base/pr112431-29.c | 68 --------------
.../gcc.target/riscv/rvv/base/pr112431-30.c | 51 ----------
.../gcc.target/riscv/rvv/base/pr112431-31.c | 68 --------------
.../gcc.target/riscv/rvv/base/pr112431-32.c | 51 ----------
.../gcc.target/riscv/rvv/base/pr112431-33.c | 51 ----------
7 files changed, 30 insertions(+), 426 deletions(-)
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-28.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-29.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-30.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-31.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-32.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-33.c
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unknown user pushed a change to branch master
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from c7506847c02 RISC-V: Add xfail test case for highest-number regno ternar [...]
new 16aea8c584e s390: testsuite: Remove xfail for vpopct{b,h}
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Summary of changes:
gcc/testsuite/gcc.target/s390/vxe/popcount-1.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
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unknown user pushed a change to branch master
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from cc46b6d4f3b Revert "RISC-V: Support highest-number regno overlap for wi [...]
new c7506847c02 RISC-V: Add xfail test case for highest-number regno ternar [...]
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Summary of changes:
.../gcc.target/riscv/rvv/base/pr112431-37.c | 103 +++++++++++++++++++++
.../gcc.target/riscv/rvv/base/pr112431-38.c | 82 ++++++++++++++++
2 files changed, 185 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-37.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-38.c
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unknown user pushed a change to branch master
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from c4fdbdac122 RISC-V: Add xfail test case for widening register overlap o [...]
new cc46b6d4f3b Revert "RISC-V: Support highest-number regno overlap for wi [...]
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Summary of changes:
gcc/config/riscv/vector.md | 115 ++++++++++-----------
.../gcc.target/riscv/rvv/base/pr112431-37.c | 103 ------------------
.../gcc.target/riscv/rvv/base/pr112431-38.c | 82 ---------------
3 files changed, 55 insertions(+), 245 deletions(-)
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-37.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-38.c
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unknown user pushed a change to branch master
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from ec78916bb37 Revert "RISC-V: Support widening register overlap for vf4/vf8"
new c4fdbdac122 RISC-V: Add xfail test case for widening register overlap o [...]
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Summary of changes:
.../rvv/base/{pr112431-31.c => pr112431-16.c} | 34 +++++++++++-----------
.../rvv/base/{pr112431-32.c => pr112431-17.c} | 18 ++++++------
.../rvv/base/{pr112431-33.c => pr112431-18.c} | 18 ++++++------
3 files changed, 35 insertions(+), 35 deletions(-)
copy gcc/testsuite/gcc.target/riscv/rvv/base/{pr112431-31.c => pr112431-16.c} (57%)
copy gcc/testsuite/gcc.target/riscv/rvv/base/{pr112431-32.c => pr112431-17.c} (65%)
copy gcc/testsuite/gcc.target/riscv/rvv/base/{pr112431-33.c => pr112431-18.c} (65%)
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