Tcwg-commits March 2024

tcwg-commits@lists.linaro.org

5 participants
1457 discussions

[gcc] branch master updated (59067ddf66e -> 47cdd86cd5d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 59067ddf66e Use integer_{zero,one}_node some more new 47cdd86cd5d aarch64: Sync aarch64-sys-regs.def with Binutils The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/aarch64/aarch64-sys-regs.def | 1 + 1 file changed, 1 insertion(+) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

8 months, 1 week

[newlib] branch main updated (bfe2790e7 -> 8bd6ba8f1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch main in repository newlib. from bfe2790e7 winsup/cygwin/fhandler/proc.cc: format_proc_cpuinfo() Linux 6 [...] new d06113bf8 Cygwin: readdir(3): stop support for pre-Cygwin 1.5.0 apps new 14970f264 Cygwin: dirent.h: fix a comment new 171916960 Cygwin: (mostly) drop NT4 and Samba < 3.0 support new 80f722e97 Cygwin: opendir(3): move ENOTDIR check into main function new 205190a80 Cygwin: // and //server: switch to Network Discovery new 8bd6ba8f1 Cygwin: /proc: fix mem leak in opendir in error case The 6 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: winsup/cygwin/autoload.cc | 11 +- winsup/cygwin/dir.cc | 14 +- winsup/cygwin/fhandler/disk_file.cc | 11 +- winsup/cygwin/fhandler/netdrive.cc | 481 +++++++++++++++++--------------- winsup/cygwin/fhandler/proc.cc | 2 + winsup/cygwin/fhandler/virtual.cc | 4 +- winsup/cygwin/local_includes/dirent.h | 2 +- winsup/cygwin/local_includes/fhandler.h | 1 + winsup/cygwin/release/3.6.0 | 6 + winsup/cygwin/sec/base.cc | 3 +- winsup/cygwin/uinfo.cc | 77 ++--- 11 files changed, 304 insertions(+), 308 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

8 months, 1 week

[binutils-gdb] branch master updated (8a61ee551ce -> 53ff349e553)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from 8a61ee551ce [gdb/symtab] Workaround PR gas/31115 new 35716707ebb gdb: syscalls: Update linux-defaults.xml.in new 59a83e67de2 gdb: syscalls: Update .xml.in files for some archs new 950895a209a gdb: syscalls: Update .xml files for some archs new a08dc2aa004 gdb: syscalls: Add loongarch-linux.xml.in new 65a550468cf gdb: syscalls: Generate loongarch-linux.xml new b369b90c0d8 gdb: syscalls: Add loongarch case in update-linux-from-src.sh new 53ff349e553 gdb: LoongArch: Set the correct XML syscall filename The 7 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gdb/data-directory/Makefile.in | 1 + gdb/loongarch-linux-tdep.c | 7 ++ gdb/syscalls/amd64-linux.xml | 11 +++ gdb/syscalls/amd64-linux.xml.in | 11 +++ gdb/syscalls/i386-linux.xml | 11 +++ gdb/syscalls/i386-linux.xml.in | 11 +++ gdb/syscalls/linux-defaults.xml.in | 3 + .../{aarch64-linux.xml => loongarch-linux.xml} | 76 ++++++++++++++++++--- ...aarch64-linux.xml.in => loongarch-linux.xml.in} | 78 +++++++++++++++++++--- gdb/syscalls/mips-n32-linux.xml | 11 +++ gdb/syscalls/mips-n32-linux.xml.in | 11 +++ gdb/syscalls/mips-n64-linux.xml | 11 +++ gdb/syscalls/mips-n64-linux.xml.in | 11 +++ gdb/syscalls/mips-o32-linux.xml | 11 +++ gdb/syscalls/mips-o32-linux.xml.in | 11 +++ gdb/syscalls/ppc-linux.xml | 11 +++ gdb/syscalls/ppc-linux.xml.in | 11 +++ gdb/syscalls/ppc64-linux.xml | 11 +++ gdb/syscalls/ppc64-linux.xml.in | 11 +++ gdb/syscalls/s390-linux.xml | 12 ++++ gdb/syscalls/s390-linux.xml.in | 12 ++++ gdb/syscalls/s390x-linux.xml | 12 ++++ gdb/syscalls/s390x-linux.xml.in | 12 ++++ gdb/syscalls/sparc-linux.xml | 11 +++ gdb/syscalls/sparc-linux.xml.in | 11 +++ gdb/syscalls/sparc64-linux.xml | 11 +++ gdb/syscalls/sparc64-linux.xml.in | 11 +++ gdb/syscalls/update-linux-from-src.sh | 4 ++ 28 files changed, 397 insertions(+), 18 deletions(-) copy gdb/syscalls/{aarch64-linux.xml => loongarch-linux.xml} (78%) copy gdb/syscalls/{aarch64-linux.xml.in => loongarch-linux.xml.in} (78%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

8 months, 1 week

[gcc] branch master updated (456e10f28b3 -> 59067ddf66e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 456e10f28b3 bitint: Fix handling of conditional bitfield loads [PR114365] new 59067ddf66e Use integer_{zero,one}_node some more The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/analyzer/constraint-manager.cc | 14 +++++++------- gcc/analyzer/region-model.cc | 28 ++++++++++++++-------------- gcc/cp/coroutines.cc | 4 ++-- gcc/fortran/trans-array.cc | 2 +- gcc/fortran/trans-decl.cc | 2 +- gcc/fortran/trans-expr.cc | 4 ++-- gcc/fortran/trans-intrinsic.cc | 4 ++-- gcc/fortran/trans-stmt.cc | 8 ++++---- gcc/fortran/trans.cc | 8 ++++---- gcc/objc/objc-next-runtime-abi-02.cc | 2 +- 10 files changed, 38 insertions(+), 38 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

8 months, 1 week

[gcc] branch master updated (4c276896d64 -> 456e10f28b3)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 4c276896d64 testsuite: add the case to cover the vectorization of A[(i+ [...] new 456e10f28b3 bitint: Fix handling of conditional bitfield loads [PR114365] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/gimple-lower-bitint.cc | 1 + gcc/testsuite/gcc.dg/{bitint-74.c => bitint-102.c} | 14 ++++++++------ 2 files changed, 9 insertions(+), 6 deletions(-) copy gcc/testsuite/gcc.dg/{bitint-74.c => bitint-102.c} (50%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

8 months, 1 week

[gcc] branch master updated (cd1ce3b326d -> 4c276896d64)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from cd1ce3b326d RISC-V: Introduce option -mrvv-max-lmul for RVV autovec new 5e64228fe1f system.h: rename vec_step to workaround powerpc/clang bug [ [...] new 0ba773df160 tree-ssa-loop-ch: Fix comment typos new 4c276896d64 testsuite: add the case to cover the vectorization of A[(i+ [...] The 3 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/system.h | 6 ++++++ gcc/testsuite/gcc.dg/vect/pr114322.c | 20 ++++++++++++++++++++ gcc/tree-ssa-loop-ch.cc | 4 ++-- 3 files changed, 28 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/vect/pr114322.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

8 months, 1 week

[binutils-gdb] branch master updated (8f39d04b97c -> 8a61ee551ce)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from 8f39d04b97c Automatic date update in version.in new 8a61ee551ce [gdb/symtab] Workaround PR gas/31115 The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gdb/dwarf2/cu.c | 1 + gdb/dwarf2/cu.h | 1 + gdb/dwarf2/read.c | 22 ++++++++++++++++++++++ 3 files changed, 24 insertions(+) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

8 months, 1 week

[gcc] branch master updated (6a55e39bdb1 -> cd1ce3b326d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 6a55e39bdb1 middle-end/113396 - int128 array index and value-ranges new cd1ce3b326d RISC-V: Introduce option -mrvv-max-lmul for RVV autovec The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/riscv/riscv-opts.h | 4 +- gcc/config/riscv/riscv-v.cc | 2 +- gcc/config/riscv/riscv-vector-costs.cc | 4 +- gcc/config/riscv/riscv.opt | 20 +++--- gcc/testsuite/g++.target/riscv/rvv/autovec/bug-2.C | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul-ice-1.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul-ice-2.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c | 2 +- .../costmodel/riscv/rvv/dynamic-lmul-mixed-1.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul1-1.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul1-2.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul1-3.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul1-4.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul1-5.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul1-6.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul1-7.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul2-1.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul2-2.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul2-3.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul2-4.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul2-5.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul2-6.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul2-7.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul4-1.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul4-10.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul4-11.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul4-12.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul4-2.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul4-3.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul4-5.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul4-6.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul4-7.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul4-8.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul4-9.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul8-1.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul8-10.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul8-11.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul8-12.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul8-13.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul8-14.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul8-2.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul8-3.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul8-4.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul8-5.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul8-6.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul8-7.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul8-8.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul8-9.c | 2 +- .../vect/costmodel/riscv/rvv/no-dynamic-lmul-1.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr111317.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr111848.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113247-1.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113281-3.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113281-5.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr114264.c | 2 +- .../vect/costmodel/riscv/rvv/vla_vs_vls-10.c | 2 +- .../vect/costmodel/riscv/rvv/vla_vs_vls-11.c | 2 +- .../vect/costmodel/riscv/rvv/vla_vs_vls-12.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-2.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-3.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-4.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-5.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-6.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-7.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-9.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c | 2 +- .../gcc.target/riscv/rvv/autovec/cmp/cmp_vi-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/cmp/cmp_vi-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/cmp/cmp_vi-7.c | 2 +- .../gcc.target/riscv/rvv/autovec/cmp/cmp_vi-8.c | 2 +- .../riscv/rvv/autovec/cond/cond_widen_reduc-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_widen_reduc-2.c | 2 +- .../rvv/autovec/cond/cond_widen_reduc_run-1.c | 2 +- .../rvv/autovec/cond/cond_widen_reduc_run-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/fold-min-poly.c | 2 +- .../riscv/rvv/autovec/partial/gimple_fold-1.c | 2 +- .../riscv/rvv/autovec/partial/select_vl-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/partial/slp-1.c | 8 +-- .../gcc.target/riscv/rvv/autovec/partial/slp-16.c | 6 +- .../gcc.target/riscv/rvv/autovec/partial/slp-17.c | 6 +- .../gcc.target/riscv/rvv/autovec/partial/slp-18.c | 6 +- .../gcc.target/riscv/rvv/autovec/partial/slp-19.c | 6 +- .../gcc.target/riscv/rvv/autovec/partial/slp-2.c | 4 +- .../gcc.target/riscv/rvv/autovec/partial/slp-3.c | 4 +- .../gcc.target/riscv/rvv/autovec/partial/slp-4.c | 4 +- .../gcc.target/riscv/rvv/autovec/partial/slp-5.c | 4 +- .../gcc.target/riscv/rvv/autovec/partial/slp-6.c | 4 +- .../gcc.target/riscv/rvv/autovec/pr112450.c | 2 +- .../gcc.target/riscv/rvv/autovec/pr112598-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/pr112598-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/pr112694-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/pr112999.c | 2 +- .../gcc.target/riscv/rvv/autovec/pr113393-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/series-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/series_run-1.c | 2 +- .../riscv/rvv/autovec/slp-interleave-1.c | 2 +- .../riscv/rvv/autovec/slp-interleave-2.c | 2 +- .../riscv/rvv/autovec/slp-interleave-3.c | 2 +- .../riscv/rvv/autovec/slp-interleave-4.c | 2 +- .../rvv/autovec/unop/math-lroundf16-rv64-ice-1.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/bitmask-10.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/bitmask-12.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/bitmask-13.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/bitmask-14.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/bitmask-5.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/bitmask-6.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/bitmask-7.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/bitmask-8.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/bitmask-9.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/trailing-1.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/trailing-2.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/trailing_run-1.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/trailing_run-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/abs-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/abs-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/and-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/and-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/and-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/avg-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/avg-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/avg-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/avg-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/avg-5.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/avg-6.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/bswap16-0.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cmp-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cmp-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cmp-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cmp-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cmp-5.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cmp-6.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/combine-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/combine-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/combine-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/combine-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/combine-5.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/combine-6.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/combine-7.c | 2 +- .../riscv/rvv/autovec/vls/combine-merge-1.c | 2 +- .../riscv/rvv/autovec/vls/combine-merge-10.c | 2 +- .../riscv/rvv/autovec/vls/combine-merge-11.c | 2 +- .../riscv/rvv/autovec/vls/combine-merge-12.c | 2 +- .../riscv/rvv/autovec/vls/combine-merge-13.c | 2 +- .../riscv/rvv/autovec/vls/combine-merge-14.c | 2 +- .../riscv/rvv/autovec/vls/combine-merge-2.c | 2 +- .../riscv/rvv/autovec/vls/combine-merge-3.c | 2 +- .../riscv/rvv/autovec/vls/combine-merge-4.c | 2 +- .../riscv/rvv/autovec/vls/combine-merge-5.c | 2 +- .../riscv/rvv/autovec/vls/combine-merge-6.c | 2 +- .../riscv/rvv/autovec/vls/combine-merge-7.c | 2 +- .../riscv/rvv/autovec/vls/combine-merge-8.c | 2 +- .../riscv/rvv/autovec/vls/combine-merge-9.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/compress-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/compress-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/compress-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/compress-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/compress-5.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/compress-6.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_abs-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_add-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_add-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_and-1.c | 2 +- .../riscv/rvv/autovec/vls/cond_convert-1.c | 2 +- .../riscv/rvv/autovec/vls/cond_convert-10.c | 2 +- .../riscv/rvv/autovec/vls/cond_convert-11.c | 2 +- .../riscv/rvv/autovec/vls/cond_convert-12.c | 2 +- .../riscv/rvv/autovec/vls/cond_convert-2.c | 2 +- .../riscv/rvv/autovec/vls/cond_convert-3.c | 2 +- .../riscv/rvv/autovec/vls/cond_convert-4.c | 2 +- .../riscv/rvv/autovec/vls/cond_convert-5.c | 2 +- .../riscv/rvv/autovec/vls/cond_convert-6.c | 2 +- .../riscv/rvv/autovec/vls/cond_convert-7.c | 2 +- .../riscv/rvv/autovec/vls/cond_convert-8.c | 2 +- .../riscv/rvv/autovec/vls/cond_convert-9.c | 2 +- .../riscv/rvv/autovec/vls/cond_copysign-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_div-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_div-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_ext-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_ext-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_ext-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_ext-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_ext-5.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_max-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_max-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_min-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_min-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_mulh-1.c | 2 +- .../riscv/rvv/autovec/vls/cond_narrow-1.c | 2 +- .../riscv/rvv/autovec/vls/cond_narrow-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_not-1.c | 2 +- .../riscv/rvv/autovec/vls/cond_shift-1.c | 2 +- .../riscv/rvv/autovec/vls/cond_shift-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_sqrt-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c | 2 +- .../riscv/rvv/autovec/vls/cond_trunc-1.c | 2 +- .../riscv/rvv/autovec/vls/cond_trunc-2.c | 2 +- .../riscv/rvv/autovec/vls/cond_trunc-3.c | 2 +- .../riscv/rvv/autovec/vls/cond_trunc-4.c | 2 +- .../riscv/rvv/autovec/vls/cond_trunc-5.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_wadd-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_wadd-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_wadd-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_wadd-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_wfma-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_wfma-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_wfms-1.c | 2 +- .../riscv/rvv/autovec/vls/cond_wfnma-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_wmul-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_wmul-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_wmul-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_wsub-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_wsub-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_wsub-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_wsub-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c | 2 +- .../riscv/rvv/autovec/vls/consecutive-1.c | 2 +- .../riscv/rvv/autovec/vls/consecutive-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/const-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/const-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/const-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/const-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/const-5.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/convert-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/convert-10.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/convert-11.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/convert-12.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/convert-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/convert-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/convert-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/convert-5.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/convert-6.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/convert-7.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/convert-8.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/convert-9.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/cvt-0.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/div-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/dup-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/dup-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/dup-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/dup-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/dup-5.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/dup-6.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/dup-7.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/ext-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/ext-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/ext-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/ext-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/ext-5.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/extract-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/extract-2.c | 2 +- .../riscv/rvv/autovec/vls/floating-point-add-1.c | 2 +- .../riscv/rvv/autovec/vls/floating-point-add-2.c | 2 +- .../riscv/rvv/autovec/vls/floating-point-add-3.c | 2 +- .../riscv/rvv/autovec/vls/floating-point-div-1.c | 2 +- .../riscv/rvv/autovec/vls/floating-point-div-2.c | 2 +- .../riscv/rvv/autovec/vls/floating-point-div-3.c | 2 +- .../riscv/rvv/autovec/vls/floating-point-max-1.c | 2 +- .../riscv/rvv/autovec/vls/floating-point-max-2.c | 2 +- .../riscv/rvv/autovec/vls/floating-point-max-3.c | 2 +- .../riscv/rvv/autovec/vls/floating-point-max-4.c | 2 +- .../riscv/rvv/autovec/vls/floating-point-max-5.c | 2 +- .../riscv/rvv/autovec/vls/floating-point-min-1.c | 2 +- .../riscv/rvv/autovec/vls/floating-point-min-2.c | 2 +- .../riscv/rvv/autovec/vls/floating-point-min-3.c | 2 +- .../riscv/rvv/autovec/vls/floating-point-min-4.c | 2 +- .../riscv/rvv/autovec/vls/floating-point-min-5.c | 2 +- .../riscv/rvv/autovec/vls/floating-point-mul-1.c | 2 +- .../riscv/rvv/autovec/vls/floating-point-mul-2.c | 2 +- .../riscv/rvv/autovec/vls/floating-point-mul-3.c | 2 +- .../riscv/rvv/autovec/vls/floating-point-sgnj-1.c | 2 +- .../riscv/rvv/autovec/vls/floating-point-sgnj-2.c | 2 +- .../riscv/rvv/autovec/vls/floating-point-sgnjx-1.c | 2 +- .../riscv/rvv/autovec/vls/floating-point-sgnjx-2.c | 2 +- .../riscv/rvv/autovec/vls/floating-point-sub-1.c | 2 +- .../riscv/rvv/autovec/vls/floating-point-sub-2.c | 2 +- .../riscv/rvv/autovec/vls/floating-point-sub-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/fma-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/fma-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/fma-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/fma-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/fma-5.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/fma-6.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/fma-7.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/fms-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/fms-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/fms-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/fnma-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/fnma-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/fnma-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/fnma-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/fnma-5.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/fnma-6.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/fnma-7.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/fnms-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/fnms-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/fnms-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/init-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/init-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/init-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/init-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/init-5.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/init-6.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/init-7.c | 2 +- .../riscv/rvv/autovec/vls/init-repeat-sequence-0.c | 2 +- .../riscv/rvv/autovec/vls/init-repeat-sequence-1.c | 2 +- .../riscv/rvv/autovec/vls/init-repeat-sequence-2.c | 2 +- .../riscv/rvv/autovec/vls/init-repeat-sequence-3.c | 2 +- .../riscv/rvv/autovec/vls/init-repeat-sequence-4.c | 2 +- .../riscv/rvv/autovec/vls/init-repeat-sequence-5.c | 2 +- .../riscv/rvv/autovec/vls/init-repeat-sequence-6.c | 2 +- .../riscv/rvv/autovec/vls/init-repeat-sequence-7.c | 2 +- .../riscv/rvv/autovec/vls/init-repeat-sequence-8.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/ior-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/ior-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/ior-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/mask-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/mask-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/mask-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/math-ceil-1.c | 2 +- .../riscv/rvv/autovec/vls/math-floor-1.c | 2 +- .../riscv/rvv/autovec/vls/math-iceil-0.c | 2 +- .../riscv/rvv/autovec/vls/math-iceil-1.c | 2 +- .../riscv/rvv/autovec/vls/math-ifloor-0.c | 2 +- .../riscv/rvv/autovec/vls/math-ifloor-1.c | 2 +- .../riscv/rvv/autovec/vls/math-irint-0.c | 2 +- .../riscv/rvv/autovec/vls/math-irint-1.c | 2 +- .../riscv/rvv/autovec/vls/math-iround-0.c | 2 +- .../riscv/rvv/autovec/vls/math-iround-1.c | 2 +- .../riscv/rvv/autovec/vls/math-lceil-0.c | 2 +- .../riscv/rvv/autovec/vls/math-lceil-1.c | 2 +- .../riscv/rvv/autovec/vls/math-lceil-rv32-0.c | 2 +- .../riscv/rvv/autovec/vls/math-lceilf-rv64-0.c | 2 +- .../riscv/rvv/autovec/vls/math-lfloor-0.c | 2 +- .../riscv/rvv/autovec/vls/math-lfloor-1.c | 2 +- .../riscv/rvv/autovec/vls/math-lfloor-rv32-0.c | 2 +- .../riscv/rvv/autovec/vls/math-lfloorf-rv64-0.c | 2 +- .../riscv/rvv/autovec/vls/math-llceil-0.c | 2 +- .../riscv/rvv/autovec/vls/math-llceilf-0.c | 2 +- .../riscv/rvv/autovec/vls/math-llfloor-0.c | 2 +- .../riscv/rvv/autovec/vls/math-llfloorf-0.c | 2 +- .../riscv/rvv/autovec/vls/math-llrint-0.c | 2 +- .../riscv/rvv/autovec/vls/math-llrintf-0.c | 2 +- .../riscv/rvv/autovec/vls/math-llrintf16-0.c | 2 +- .../riscv/rvv/autovec/vls/math-llround-0.c | 2 +- .../riscv/rvv/autovec/vls/math-llroundf-0.c | 2 +- .../riscv/rvv/autovec/vls/math-llroundf16-0.c | 2 +- .../riscv/rvv/autovec/vls/math-lrint-0.c | 2 +- .../riscv/rvv/autovec/vls/math-lrint-1.c | 2 +- .../riscv/rvv/autovec/vls/math-lrint-rv32-0.c | 2 +- .../riscv/rvv/autovec/vls/math-lrintf-rv64-0.c | 2 +- .../riscv/rvv/autovec/vls/math-lrintf16-rv32-0.c | 2 +- .../riscv/rvv/autovec/vls/math-lrintf16-rv64-0.c | 2 +- .../riscv/rvv/autovec/vls/math-lround-0.c | 2 +- .../riscv/rvv/autovec/vls/math-lround-1.c | 2 +- .../riscv/rvv/autovec/vls/math-lround-rv32-0.c | 2 +- .../riscv/rvv/autovec/vls/math-lroundf-rv64-0.c | 2 +- .../riscv/rvv/autovec/vls/math-lroundf16-rv32-0.c | 2 +- .../riscv/rvv/autovec/vls/math-lroundf16-rv64-0.c | 2 +- .../riscv/rvv/autovec/vls/math-nearbyint-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/math-rint-1.c | 2 +- .../riscv/rvv/autovec/vls/math-round-1.c | 2 +- .../riscv/rvv/autovec/vls/math-roundeven-1.c | 2 +- .../riscv/rvv/autovec/vls/math-trunc-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/max-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/merge-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/merge-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/merge-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/merge-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/merge-5.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/merge-6.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/merge-7.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/min-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/minus-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/minus-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/minus-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/misalign-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/mod-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/mov-1.c | 2 +- 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| 2 +- .../gcc.target/riscv/rvv/autovec/vls/neg-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/not-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/perm-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/perm-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/perm-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/perm-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/perm-5.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/perm-6.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/perm-7.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/plus-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/plus-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/plus-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/reduc-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/reduc-10.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/reduc-11.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/reduc-12.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/reduc-13.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/reduc-14.c | 2 +- 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.../gcc.target/riscv/rvv/autovec/vls/vec-set-11.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/vec-set-12.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/vec-set-13.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/vec-set-14.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/vec-set-15.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/vec-set-16.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/vec-set-17.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/vec-set-18.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/vec-set-19.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/vec-set-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/vec-set-20.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/vec-set-21.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/vec-set-22.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/vec-set-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/vec-set-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/vec-set-5.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/vec-set-6.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/vec-set-7.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/vec-set-8.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/vec-set-9.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/wadd-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/wadd-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/wadd-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/wadd-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/wfma-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/wfma-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/wfma-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/wfms-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/wfnma-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/wfnms-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/wmul-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/wmul-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/wmul-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/wred-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/wred-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/wred-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/wsub-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/wsub-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/wsub-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/vls/wsub-4.c | 2 +- .../riscv/rvv/autovec/widen/widen_reduc-1.c | 2 +- .../riscv/rvv/autovec/widen/widen_reduc_order-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve32f-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve32x-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve64d-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve64f-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve64x-3.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c | 4 +- gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c | 6 +- gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 72 +++++++++++----------- .../gcc.target/riscv/rvv/vsetvl/pr111255.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c | 2 +- 547 files changed, 612 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8 months, 1 week

[gcc] branch master updated (994d8f922b9 -> 6a55e39bdb1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 994d8f922b9 LoongArch: Combine UNITS_PER_FP_REG and UNITS_PER_FPREG macros. new 6a55e39bdb1 middle-end/113396 - int128 array index and value-ranges The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/testsuite/gcc.dg/torture/pr113396.c | 19 +++++++++++++++++++ gcc/tree-dfa.cc | 6 ++++-- 2 files changed, 23 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/torture/pr113396.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

8 months, 1 week

[gcc] branch releases/gcc-13 updated (77f94f0f59a -> 51e2f7a22e8)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch releases/gcc-13 in repository gcc. from 77f94f0f59a Daily bump. new 86183487993 libstdc++: Fix _Safe_local_iterator<>::_M_valid_range new 51e2f7a22e8 libstdc++: Fix N3344 behavior on _Safe_iterator::_M_can_advance The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: libstdc++-v3/include/debug/safe_iterator.tcc | 3 +++ libstdc++-v3/include/debug/safe_local_iterator.tcc | 8 ++++++- .../23_containers/unordered_set/debug/114316.cc | 28 ++++++++++++++++++++++ .../vector/debug/{114316.cc => n3644.cc} | 6 ++--- 4 files changed, 41 insertions(+), 4 deletions(-) create mode 100644 libstdc++-v3/testsuite/23_containers/unordered_set/debug/114316.cc copy libstdc++-v3/testsuite/23_containers/vector/debug/{114316.cc => n3644.cc} (75%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

8 months, 1 week

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