Tcwg-commits December 2024

tcwg-commits@lists.linaro.org

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1571 discussions

[glibc] branch release/2.40/master updated (091dd12831 -> c6cdab1e01)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch release/2.40/master in repository glibc. from 091dd12831 nptl: initialize cpu_id_start prior to rseq registration new c6cdab1e01 malloc: add indirection for malloc(-like) functions in tests [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: malloc/tst-aligned-alloc.c | 2 ++ malloc/tst-compathooks-off.c | 2 ++ ...lloc-random-thread-cross.c => tst-malloc-aux.h} | 28 +++++++++++++++++++--- malloc/tst-malloc-check.c | 2 ++ malloc/tst-malloc-too-large.c | 1 + malloc/tst-malloc.c | 2 ++ malloc/tst-realloc.c | 2 ++ support/support.h | 2 +- test-skeleton.c | 1 - 9 files changed, 37 insertions(+), 5 deletions(-) copy malloc/{tst-aligned-alloc-random-thread-cross.c => tst-malloc-aux.h} (53%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 months, 2 weeks

[glibc] branch release/2.39/master updated (aa8768999e -> 51da74a97e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch release/2.39/master in repository glibc. from aa8768999e Pass -nostdlib -nostartfiles together with -r [BZ #31753] new 51da74a97e malloc: add indirection for malloc(-like) functions in tests [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: malloc/tst-aligned-alloc.c | 2 ++ malloc/tst-compathooks-off.c | 2 ++ ...lloc-random-thread-cross.c => tst-malloc-aux.h} | 28 +++++++++++++++++++--- malloc/tst-malloc-check.c | 2 ++ malloc/tst-malloc-too-large.c | 1 + malloc/tst-malloc.c | 2 ++ malloc/tst-realloc.c | 2 ++ support/support.h | 2 +- test-skeleton.c | 1 - 9 files changed, 37 insertions(+), 5 deletions(-) copy malloc/{tst-aligned-alloc-random-thread-cross.c => tst-malloc-aux.h} (53%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 months, 2 weeks

[toolchain/ci/interesting-commits] branch master updated (881a2db37 -> 1300f20ee)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch master in repository toolchain/ci/interesting-commits. from 881a2db37 Add entry f33536468b7f05c05c8cf8088427b0b5b665eb65 from https [...] new 1300f20ee Add entry f33536468b7f05c05c8cf8088427b0b5b665eb65 from https [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: llvm/sha1/f33536468b7f05c05c8cf8088427b0b5b665eb65/jira/description | 5 +++++ llvm/sha1/f33536468b7f05c05c8cf8088427b0b5b665eb65/jira/yaml | 5 +++++ llvm/sha1/f33536468b7f05c05c8cf8088427b0b5b665eb65/status.txt | 5 +++++ .../llvm-aarch64-master-O3_LTO}/details.txt | 0 .../llvm-aarch64-master-O3_LTO}/reproduction_instructions.txt | 0 .../llvm-aarch64-master-O3_LTO}/status-summary.txt | 0 .../llvm-aarch64-master-O3_LTO/status.txt | 6 +++--- .../tcwg_bmk-code_vect-spec2k6}/status-summary.txt | 0 .../tcwg_bmk-code_vect-spec2k6/status.txt | 6 +++--- 9 files changed, 21 insertions(+), 6 deletions(-) copy llvm/sha1/{ae73bc8e94b3174e2b495eee544cf843b6e51899/tcwg_bmk-code_size-spec2k [...] copy llvm/sha1/{0548481856e75998e1de329f5c9722dcf1ca5c84/tcwg_bmk-code_vect-spec2k [...] copy llvm/sha1/{ae73bc8e94b3174e2b495eee544cf843b6e51899 => f33536468b7f05c05c8cf8 [...] copy llvm/sha1/{96bb375f5cedcfcc5dcd96296ba54ff933b39d4d => f33536468b7f05c05c8cf8 [...] copy llvm/sha1/{ae73bc8e94b3174e2b495eee544cf843b6e51899 => f33536468b7f05c05c8cf8 [...] copy llvm/sha1/{3a4ccebb5c5142c15fb6d72aedadb27205ef33d5 => f33536468b7f05c05c8cf8 [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 months, 2 weeks

[toolchain/ci/interesting-commits] branch master updated (3d354879f -> 881a2db37)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch master in repository toolchain/ci/interesting-commits. from 3d354879f Add entry 28d102d15c6af7f80cb1077e098e020476d26d00 from https [...] new 881a2db37 Add entry f33536468b7f05c05c8cf8088427b0b5b665eb65 from https [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../tcwg_bmk-code_vect-spec2k6/llvm-aarch64-master-O3_LTO/build_url | 2 +- .../llvm-aarch64-master-O3_LTO}/last_good | 0 2 files changed, 1 insertion(+), 1 deletion(-) copy llvm/sha1/{1bc9b67bd87d7ec51045951c93fd5db953faa745 => f33536468b7f05c05c8cf8 [...] copy llvm/sha1/f33536468b7f05c05c8cf8088427b0b5b665eb65/{tcwg_bmk-code_size-spec2k [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 months, 2 weeks

[gcc] branch master updated (62fa2e43ccc -> 0374e677147)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 62fa2e43ccc aarch64: Fix ICE happening in SET_TYPE_VECTOR_SUBPARTS with [...] new 0374e677147 testsuite/gcc.dg/tree-ssa/pr111456-1.c: Handle fallout The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/testsuite/gcc.dg/tree-ssa/pr111456-1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 months, 2 weeks

[gcc] branch master updated (6fbff06f9e3 -> 62fa2e43ccc)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 6fbff06f9e3 RISC-V: Refine signed vector SAT_SUB testcase dump check to [...] new 62fa2e43ccc aarch64: Fix ICE happening in SET_TYPE_VECTOR_SUBPARTS with [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/aarch64/aarch64-builtins.cc | 129 ++++++++++++---------- gcc/config/aarch64/aarch64-builtins.h | 29 +++-- gcc/config/aarch64/aarch64-sve-builtins-shapes.cc | 4 +- gcc/config/aarch64/aarch64-sve-builtins.cc | 2 +- 4 files changed, 95 insertions(+), 69 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 months, 2 weeks

[gcc] branch master updated (6c41a912f5e -> 6fbff06f9e3)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 6c41a912f5e libstdc++: deprecate is_trivial for C++26 (P3247R2) new a6aa0719aaa RISC-V: Refine unsigned vector SAT_ADD testcase dump check [...] new aa8c20e32e5 RISC-V: Refine unsigned vector SAT_SUB testcase dump check [...] new b5c99314b80 RISC-V: Refine unsigned vector SAT_TRUNC testcase dump chec [...] new 1850da91610 RISC-V: Refine signed vector SAT_ADD testcase dump check to [...] new 75d518100ed RISC-V: Refine signed vector SAT_TRUNC testcase dump check [...] new 6fbff06f9e3 RISC-V: Refine signed vector SAT_SUB testcase dump check to [...] The 6 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c | 4 ++-- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c | 4 ++-- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c | 4 ++-- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c | 6 +++--- .../riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c | 4 ++-- .../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c | 4 ++-- .../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c | 4 ++-- .../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c | 4 ++-- .../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c | 4 ++-- .../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c | 4 ++-- .../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c | 4 ++-- .../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c | 4 ++-- .../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c | 4 ++-- .../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c | 4 ++-- .../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c | 4 ++-- .../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c | 4 ++-- .../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c | 4 ++-- .../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c | 4 ++-- .../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c | 4 ++-- .../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u64.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u64.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c | 8 ++++---- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u8.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u16.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u32.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u64.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u8.c | 4 ++-- 215 files changed, 512 insertions(+), 512 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 months, 2 weeks

[toolchain/ci/interesting-commits] branch master updated (749c607b5 -> 3d354879f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch master in repository toolchain/ci/interesting-commits. from 749c607b5 Add entry 28d102d15c6af7f80cb1077e098e020476d26d00 from https [...] new 3d354879f Add entry 28d102d15c6af7f80cb1077e098e020476d26d00 from https [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: glibc/glibc-2.40.9000-442-g28d102d15c | 1 + .../commit-log.txt | 8 ++--- .../jira/components | 0 .../jira/description | 19 +++++++++++ .../jira/key | 1 + .../jira/startdate | 1 + .../jira/summary | 1 + .../jira/yaml | 27 +++++++++++++++ .../status-summary.txt | 0 .../status.txt | 6 ++-- .../tcwg_glibc_check/master-aarch64/details.txt | 38 +++++++++++----------- .../master-aarch64}/reproduction_instructions.txt | 0 .../master-aarch64}/status-summary.txt | 0 .../tcwg_glibc_check/master-aarch64/status.txt | 4 +-- .../tcwg_glibc_check}/status-summary.txt | 0 .../tcwg_glibc_check/status.txt | 6 ++-- 16 files changed, 81 insertions(+), 31 deletions(-) create mode 120000 glibc/glibc-2.40.9000-442-g28d102d15c copy glibc/sha1/{f9e90e4b4ce71f88470c8c8b0a16c21088294be4 => 28d102d15c6af7f80cb10 [...] copy glibc/sha1/{026a84a54d3b6c23b999b793e2a6f8ecd211e3b8 => 28d102d15c6af7f80cb10 [...] create mode 100644 glibc/sha1/28d102d15c6af7f80cb1077e098e020476d26d00/jira/description create mode 100644 glibc/sha1/28d102d15c6af7f80cb1077e098e020476d26d00/jira/key create mode 100644 glibc/sha1/28d102d15c6af7f80cb1077e098e020476d26d00/jira/startdate create mode 100644 glibc/sha1/28d102d15c6af7f80cb1077e098e020476d26d00/jira/summary create mode 100644 glibc/sha1/28d102d15c6af7f80cb1077e098e020476d26d00/jira/yaml copy {gcc/sha1/a1381b69b9d81f210735d4a5bc9d65a0b01d1bda/tcwg_gnu_embed_check_gcc/m [...] copy glibc/sha1/{176671f6042912200ea9733bb6cc8212e06bc85e => 28d102d15c6af7f80cb10 [...] copy glibc/sha1/{f9e90e4b4ce71f88470c8c8b0a16c21088294be4 => 28d102d15c6af7f80cb10 [...] copy {gcc/sha1/113e902e842b9b6d038162dfa751c25377b594d3/tcwg_gnu_embed_check_gcc/m [...] copy {gcc/sha1/a1381b69b9d81f210735d4a5bc9d65a0b01d1bda/tcwg_gnu_embed_check_gcc/m [...] copy glibc/sha1/{776938e8b8dcf2b59998979e91cc0f9db7d771a8 => 28d102d15c6af7f80cb10 [...] copy {gcc/sha1/a1381b69b9d81f210735d4a5bc9d65a0b01d1bda/tcwg_gnu_embed_check_gcc/m [...] copy glibc/sha1/{176671f6042912200ea9733bb6cc8212e06bc85e => 28d102d15c6af7f80cb10 [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 months, 2 weeks

[toolchain/ci/interesting-commits] branch master updated (0469693a7 -> 749c607b5)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch master in repository toolchain/ci/interesting-commits. from 0469693a7 Add entry 75e7d1600f47859df40b2ac0feff5a71e0dbb040 from https [...] new 749c607b5 Add entry 28d102d15c6af7f80cb1077e098e020476d26d00 from https [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../first_url | 2 +- .../tcwg_glibc_check/master-aarch64/build_url | 2 +- .../tcwg_glibc_check}/master-aarch64/last_good | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) copy glibc/sha1/{0ae0af68d8fa3bf6cbe1e4f1de5929ff71de67b3 => 28d102d15c6af7f80cb10 [...] copy glibc/sha1/{30379efad117b85cc56a255cac628d0ad745bfe3 => 28d102d15c6af7f80cb10 [...] copy {gdb/sha1/922ab963e1c48c364b7f6363cb8e19f8a7175a20/tcwg_gdb_check => glibc/sh [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 months, 2 weeks

[glibc] branch master updated (28d102d15c -> a9944a52c9)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository glibc. from 28d102d15c Implement C23 acospi new a9944a52c9 malloc: add indirection for malloc(-like) functions in tests [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: malloc/tst-aligned-alloc.c | 2 ++ malloc/tst-compathooks-off.c | 2 ++ ...lloc-random-thread-cross.c => tst-malloc-aux.h} | 28 +++++++++++++++++++--- malloc/tst-malloc-check.c | 2 ++ malloc/tst-malloc-too-large.c | 1 + malloc/tst-malloc.c | 2 ++ malloc/tst-realloc.c | 2 ++ support/support.h | 2 +- test-skeleton.c | 1 - 9 files changed, 37 insertions(+), 5 deletions(-) copy malloc/{tst-aligned-alloc-random-thread-cross.c => tst-malloc-aux.h} (53%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 months, 2 weeks

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