Tcwg-commits November 2024

tcwg-commits@lists.linaro.org

3 participants
1843 discussions

[toolchain/ci/interesting-commits] branch master updated (392fddee7 -> c0d18a3ab)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch master in repository toolchain/ci/interesting-commits. from 392fddee7 Add entry beec291225be9b5e7a60b6818cf80224c343811d from https [...] new c0d18a3ab Add entry beec291225be9b5e7a60b6818cf80224c343811d from https [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../commit-log.txt | 2 +- .../jira/description | 6 +++- .../jira/summary | 2 +- .../jira/yaml | 8 ++++-- .../status.txt | 4 +++ .../details.txt | 33 +++++----------------- .../reproduction_instructions.txt | 4 +-- .../reproduction_instructions_with_ci_script.txt | 4 +-- .../status-summary.txt | 0 .../master-aarch64-check_bootstrap_lto/status.txt | 2 ++ .../tcwg_bootstrap_check}/status-summary.txt | 0 .../tcwg_bootstrap_check/status.txt | 3 ++ 12 files changed, 33 insertions(+), 35 deletions(-) copy gcc/sha1/{19f630e6ae8da7159a8c82f337b699245f66e6a6/tcwg_gcc_check/master-aarc [...] copy gcc/sha1/beec291225be9b5e7a60b6818cf80224c343811d/{tcwg_gnu_native_check_gcc/ [...] copy gcc/sha1/beec291225be9b5e7a60b6818cf80224c343811d/{tcwg_gnu_cross_check_gcc/m [...] copy gcc/sha1/{0b27a7dd050262a7d64d87863201e4ebbde88386 => beec291225be9b5e7a60b68 [...] create mode 100644 gcc/sha1/beec291225be9b5e7a60b6818cf80224c343811d/tcwg_bootstra [...] copy gcc/sha1/{0b27a7dd050262a7d64d87863201e4ebbde88386 => beec291225be9b5e7a60b68 [...] create mode 100644 gcc/sha1/beec291225be9b5e7a60b6818cf80224c343811d/tcwg_bootstra [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 months, 3 weeks

[toolchain/ci/interesting-commits] branch master updated (157f5d9e3 -> 392fddee7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch master in repository toolchain/ci/interesting-commits. from 157f5d9e3 Add entry beec291225be9b5e7a60b6818cf80224c343811d from https [...] new 392fddee7 Add entry beec291225be9b5e7a60b6818cf80224c343811d from https [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../tcwg_bootstrap_check/master-aarch64-check_bootstrap_lto}/build_url | 2 +- .../master-aarch64-check_bootstrap_lto}/last_good | 0 2 files changed, 1 insertion(+), 1 deletion(-) copy gcc/sha1/{02917ac4528e32d1b2d0da5f45ef5937c56942cd/tcwg_bootstrap_check/maste [...] copy gcc/sha1/beec291225be9b5e7a60b6818cf80224c343811d/{tcwg_gcc_check/master-aarc [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 months, 3 weeks

[gcc] branch master updated (237380cdec2 -> 70ec3d20bfb)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 237380cdec2 fortran: Evaluate once BACK argument of MINLOC/MAXLOC with [...] new 12c60ff1ffd aarch64: Rework sme_2mode_function insns new 33812137800 aarch64: Refactor SVE predicated-to-unpredicated splits new 3e582f8c797 aarch64: Rename some SME iterators new 164fbe01d59 aarch64: Fix the choice of unspec in two SME patterns new 648fc673e68 aarch64: Add support for SVE_B16B16 new e6751e1deb6 aarch64: Add support for SME_F16F16 new cdacb32bd5c aarch64: Add support for SME_B16B16 new 70ec3d20bfb aarch64: Add support for SME2p1 The 8 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/aarch64/aarch64-c.cc | 9 + gcc/config/aarch64/aarch64-option-extensions.def | 9 + gcc/config/aarch64/aarch64-sme.md | 414 ++++++++++++++++----- gcc/config/aarch64/aarch64-sve-builtins-base.cc | 5 +- .../aarch64/aarch64-sve-builtins-functions.h | 15 +- gcc/config/aarch64/aarch64-sve-builtins-shapes.cc | 11 + gcc/config/aarch64/aarch64-sve-builtins-shapes.h | 1 + gcc/config/aarch64/aarch64-sve-builtins-sme.cc | 61 ++- gcc/config/aarch64/aarch64-sve-builtins-sme.def | 41 ++ gcc/config/aarch64/aarch64-sve-builtins-sme.h | 3 + gcc/config/aarch64/aarch64-sve-builtins-sve2.cc | 11 + gcc/config/aarch64/aarch64-sve-builtins-sve2.def | 32 ++ gcc/config/aarch64/aarch64-sve-builtins-sve2.h | 1 + gcc/config/aarch64/aarch64-sve-builtins.cc | 27 +- gcc/config/aarch64/aarch64-sve.md | 408 ++++++++++---------- gcc/config/aarch64/aarch64-sve2.md | 101 +++-- gcc/config/aarch64/aarch64.cc | 6 +- gcc/config/aarch64/aarch64.h | 19 + gcc/config/aarch64/aarch64.md | 29 +- gcc/config/aarch64/iterators.md | 102 ++++- gcc/config/aarch64/predicates.md | 1 + gcc/doc/invoke.texi | 18 +- .../gcc.target/aarch64/pragma_cpp_predefs_4.c | 99 ++++- .../aarch64/sme2/acle-asm/add_za16_bf16_vg1x2.c | 126 +++++++ .../aarch64/sme2/acle-asm/add_za16_bf16_vg1x4.c | 141 +++++++ .../aarch64/sme2/acle-asm/add_za16_f16_vg1x2.c | 126 +++++++ .../aarch64/sme2/acle-asm/add_za16_f16_vg1x4.c | 141 +++++++ .../aarch64/sme2/acle-asm/clamp_bf16_x2.c | 98 +++++ .../aarch64/sme2/acle-asm/clamp_bf16_x4.c | 108 ++++++ .../aarch64/sme2/acle-asm/cvt_f32_f16_x2.c | 54 +++ .../aarch64/sme2/acle-asm/cvtl_f32_f16_x2.c | 54 +++ .../gcc.target/aarch64/sme2/acle-asm/max_bf16_x2.c | 211 +++++++++++ .../gcc.target/aarch64/sme2/acle-asm/max_bf16_x4.c | 253 +++++++++++++ .../aarch64/sme2/acle-asm/maxnm_bf16_x2.c | 211 +++++++++++ .../aarch64/sme2/acle-asm/maxnm_bf16_x4.c | 253 +++++++++++++ .../gcc.target/aarch64/sme2/acle-asm/min_bf16_x2.c | 211 +++++++++++ .../gcc.target/aarch64/sme2/acle-asm/min_bf16_x4.c | 253 +++++++++++++ .../aarch64/sme2/acle-asm/minnm_bf16_x2.c | 211 +++++++++++ .../aarch64/sme2/acle-asm/minnm_bf16_x4.c | 253 +++++++++++++ .../sme2/acle-asm/mla_lane_za16_bf16_vg1x2.c | 106 ++++++ .../sme2/acle-asm/mla_lane_za16_bf16_vg1x4.c | 112 ++++++ .../sme2/acle-asm/mla_lane_za16_f16_vg1x2.c | 106 ++++++ .../sme2/acle-asm/mla_lane_za16_f16_vg1x4.c | 112 ++++++ .../aarch64/sme2/acle-asm/mla_za16_bf16_vg1x2.c | 184 +++++++++ .../aarch64/sme2/acle-asm/mla_za16_bf16_vg1x4.c | 176 +++++++++ .../aarch64/sme2/acle-asm/mla_za16_f16_vg1x2.c | 184 +++++++++ .../aarch64/sme2/acle-asm/mla_za16_f16_vg1x4.c | 176 +++++++++ .../sme2/acle-asm/mls_lane_za16_bf16_vg1x2.c | 106 ++++++ .../sme2/acle-asm/mls_lane_za16_bf16_vg1x4.c | 112 ++++++ .../sme2/acle-asm/mls_lane_za16_f16_vg1x2.c | 106 ++++++ .../sme2/acle-asm/mls_lane_za16_f16_vg1x4.c | 112 ++++++ .../aarch64/sme2/acle-asm/mls_za16_bf16_vg1x2.c | 184 +++++++++ .../aarch64/sme2/acle-asm/mls_za16_bf16_vg1x4.c | 176 +++++++++ .../aarch64/sme2/acle-asm/mls_za16_f16_vg1x2.c | 184 +++++++++ .../aarch64/sme2/acle-asm/mls_za16_f16_vg1x4.c | 176 +++++++++ .../aarch64/sme2/acle-asm/mopa_za16_bf16.c | 34 ++ .../aarch64/sme2/acle-asm/mopa_za16_f16.c | 34 ++ .../aarch64/sme2/acle-asm/mops_za16_bf16.c | 34 ++ .../aarch64/sme2/acle-asm/mops_za16_f16.c | 34 ++ .../aarch64/sme2/acle-asm/readz_hor_za128.c | 187 ++++++++++ .../aarch64/sme2/acle-asm/readz_hor_za16.c | 127 +++++++ .../aarch64/sme2/acle-asm/readz_hor_za16_vg2.c | 144 +++++++ .../aarch64/sme2/acle-asm/readz_hor_za16_vg4.c | 142 +++++++ .../aarch64/sme2/acle-asm/readz_hor_za32.c | 137 +++++++ .../aarch64/sme2/acle-asm/readz_hor_za32_vg2.c | 116 ++++++ .../aarch64/sme2/acle-asm/readz_hor_za32_vg4.c | 133 +++++++ .../aarch64/sme2/acle-asm/readz_hor_za64.c | 127 +++++++ .../aarch64/sme2/acle-asm/readz_hor_za64_vg2.c | 117 ++++++ .../aarch64/sme2/acle-asm/readz_hor_za64_vg4.c | 133 +++++++ .../aarch64/sme2/acle-asm/readz_hor_za8.c | 87 +++++ .../aarch64/sme2/acle-asm/readz_hor_za8_vg2.c | 144 +++++++ .../aarch64/sme2/acle-asm/readz_hor_za8_vg4.c | 160 ++++++++ .../aarch64/sme2/acle-asm/readz_ver_za16.c | 127 +++++++ .../aarch64/sme2/acle-asm/readz_ver_za16_vg2.c | 144 +++++++ .../aarch64/sme2/acle-asm/readz_ver_za16_vg4.c | 142 +++++++ .../aarch64/sme2/acle-asm/readz_ver_za32.c | 137 +++++++ .../aarch64/sme2/acle-asm/readz_ver_za32_vg2.c | 116 ++++++ .../aarch64/sme2/acle-asm/readz_ver_za32_vg4.c | 133 +++++++ .../aarch64/sme2/acle-asm/readz_ver_za64.c | 127 +++++++ .../aarch64/sme2/acle-asm/readz_ver_za64_vg2.c | 117 ++++++ .../aarch64/sme2/acle-asm/readz_ver_za64_vg4.c | 133 +++++++ .../aarch64/sme2/acle-asm/readz_ver_za8.c | 87 +++++ .../aarch64/sme2/acle-asm/readz_ver_za8_vg2.c | 144 +++++++ .../aarch64/sme2/acle-asm/readz_ver_za8_vg4.c | 160 ++++++++ .../aarch64/sme2/acle-asm/readz_za16_vg1x2.c | 126 +++++++ .../aarch64/sme2/acle-asm/readz_za16_vg1x4.c | 141 +++++++ .../aarch64/sme2/acle-asm/readz_za32_vg1x2.c | 126 +++++++ .../aarch64/sme2/acle-asm/readz_za32_vg1x4.c | 141 +++++++ .../aarch64/sme2/acle-asm/readz_za64_vg1x2.c | 126 +++++++ .../aarch64/sme2/acle-asm/readz_za64_vg1x4.c | 141 +++++++ .../aarch64/sme2/acle-asm/readz_za8_vg1x2.c | 126 +++++++ .../aarch64/sme2/acle-asm/readz_za8_vg1x4.c | 141 +++++++ .../aarch64/sme2/acle-asm/sub_za16_bf16_vg1x2.c | 126 +++++++ .../aarch64/sme2/acle-asm/sub_za16_bf16_vg1x4.c | 141 +++++++ .../aarch64/sme2/acle-asm/sub_za16_f16_vg1x2.c | 126 +++++++ .../aarch64/sme2/acle-asm/sub_za16_f16_vg1x4.c | 141 +++++++ .../aarch64/sme2/acle-asm/zero_za64_vg1x2.c | 97 +++++ .../aarch64/sme2/acle-asm/zero_za64_vg1x4.c | 97 +++++ .../aarch64/sme2/acle-asm/zero_za64_vg2x1.c | 117 ++++++ .../aarch64/sme2/acle-asm/zero_za64_vg2x2.c | 97 +++++ .../aarch64/sme2/acle-asm/zero_za64_vg2x4.c | 97 +++++ .../aarch64/sme2/acle-asm/zero_za64_vg4x1.c | 127 +++++++ .../aarch64/sme2/acle-asm/zero_za64_vg4x2.c | 97 +++++ .../aarch64/sme2/acle-asm/zero_za64_vg4x4.c | 97 +++++ .../aarch64/sve/acle/asm/test_sve_acle.h | 16 + .../gcc.target/aarch64/sve/bf16_arith_1.c | 10 + .../gcc.target/aarch64/sve/bf16_arith_1.h | 24 ++ .../gcc.target/aarch64/sve/bf16_arith_2.c | 8 + .../gcc.target/aarch64/sve/bf16_arith_3.c | 8 + gcc/testsuite/gcc.target/aarch64/sve/cond_mla_9.c | 25 ++ gcc/testsuite/gcc.target/aarch64/sve/fmad_1.c | 9 +- gcc/testsuite/gcc.target/aarch64/sve/fmla_1.c | 9 +- gcc/testsuite/gcc.target/aarch64/sve/fmls_1.c | 9 +- gcc/testsuite/gcc.target/aarch64/sve/fmsb_1.c | 9 +- .../gcc.target/aarch64/sve2/acle/asm/add_bf16.c | 315 ++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/clamp_bf16.c | 49 +++ .../gcc.target/aarch64/sve2/acle/asm/max_bf16.c | 301 +++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/maxnm_bf16.c | 301 +++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/min_bf16.c | 301 +++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/minnm_bf16.c | 301 +++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/mla_bf16.c | 341 +++++++++++++++++ .../aarch64/sve2/acle/asm/mla_lane_bf16.c | 135 +++++++ .../gcc.target/aarch64/sve2/acle/asm/mls_bf16.c | 341 +++++++++++++++++ .../aarch64/sve2/acle/asm/mls_lane_bf16.c | 135 +++++++ .../gcc.target/aarch64/sve2/acle/asm/mul_bf16.c | 315 ++++++++++++++++ .../aarch64/sve2/acle/asm/mul_lane_bf16.c | 121 ++++++ .../gcc.target/aarch64/sve2/acle/asm/sub_bf16.c | 304 +++++++++++++++ gcc/testsuite/lib/target-supports.exp | 3 +- 128 files changed, 15365 insertions(+), 349 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/add_za16_bf16_vg1x2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/add_za16_bf16_vg1x4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/add_za16_f16_vg1x2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/add_za16_f16_vg1x4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/clamp_bf16_x2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/clamp_bf16_x4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_f32_f16_x2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtl_f32_f16_x2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/max_bf16_x2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/max_bf16_x4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/maxnm_bf16_x2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/maxnm_bf16_x4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/min_bf16_x2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/min_bf16_x4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/minnm_bf16_x2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/minnm_bf16_x4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_bf [...] create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_bf [...] create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_f1 [...] create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_f1 [...] create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za16_bf16_vg1x2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za16_bf16_vg1x4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za16_f16_vg1x2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mla_za16_f16_vg1x4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mls_lane_za16_bf [...] create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mls_lane_za16_bf [...] create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mls_lane_za16_f1 [...] create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mls_lane_za16_f1 [...] create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mls_za16_bf16_vg1x2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mls_za16_bf16_vg1x4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mls_za16_f16_vg1x2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mls_za16_f16_vg1x4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mopa_za16_bf16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mopa_za16_f16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mops_za16_bf16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/mops_za16_f16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_hor_za128.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_hor_za16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_hor_za16_vg2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_hor_za16_vg4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_hor_za32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_hor_za32_vg2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_hor_za32_vg4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_hor_za64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_hor_za64_vg2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_hor_za64_vg4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_hor_za8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_hor_za8_vg2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_hor_za8_vg4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_ver_za16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_ver_za16_vg2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_ver_za16_vg4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_ver_za32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_ver_za32_vg2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_ver_za32_vg4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_ver_za64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_ver_za64_vg2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_ver_za64_vg4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_ver_za8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_ver_za8_vg2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_ver_za8_vg4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_za16_vg1x2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_za16_vg1x4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_za32_vg1x2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_za32_vg1x4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_za64_vg1x2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_za64_vg1x4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_za8_vg1x2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/readz_za8_vg1x4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/sub_za16_bf16_vg1x2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/sub_za16_bf16_vg1x4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/sub_za16_f16_vg1x2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/sub_za16_f16_vg1x4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/zero_za64_vg1x2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/zero_za64_vg1x4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/zero_za64_vg2x1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/zero_za64_vg2x2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/zero_za64_vg2x4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/zero_za64_vg4x1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/zero_za64_vg4x2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/zero_za64_vg4x4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/bf16_arith_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/bf16_arith_1.h create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/bf16_arith_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/bf16_arith_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_mla_9.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/add_bf16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/clamp_bf16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/max_bf16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/maxnm_bf16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/min_bf16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/minnm_bf16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mla_bf16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mla_lane_bf16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mls_bf16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mls_lane_bf16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mul_bf16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/mul_lane_bf16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sub_bf16.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 months, 3 weeks

[glibc] branch master updated (47311cca31 -> 6e7778ecde)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository glibc. from 47311cca31 manual: Add description of AArch64-specific pkey flags new ab545460b0 intl: avoid alloca for arbitrary sizes (bug 32380) new 6e7778ecde misc: remove extra va_end in error_tail (bug 32233) The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: intl/dcigettext.c | 51 ++++++++++++--------------------------------------- misc/error.c | 1 - 2 files changed, 12 insertions(+), 40 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 months, 3 weeks

[gcc] branch master updated (086ee8d0866 -> 237380cdec2)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 086ee8d0866 i386: Remove workaround for Solaris ld 64-bit TLS IE limitation new 237380cdec2 fortran: Evaluate once BACK argument of MINLOC/MAXLOC with [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/fortran/trans-intrinsic.cc | 21 +- gcc/testsuite/gfortran.dg/maxloc_8.f90 | 349 +++++++++++++++++++++++++++++++++ gcc/testsuite/gfortran.dg/minloc_9.f90 | 349 +++++++++++++++++++++++++++++++++ 3 files changed, 717 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gfortran.dg/maxloc_8.f90 create mode 100644 gcc/testsuite/gfortran.dg/minloc_9.f90 -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 months, 3 weeks

[binutils-gdb] branch master updated (661611b9d71 -> 4d1636909da)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from 661611b9d71 gdb/python: fix reference leak in gdb.BreakpointLocation.th [...] new 4d1636909da Remove Debian from SECURITY.txt The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: binutils/SECURITY.txt | 1 - 1 file changed, 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 months, 3 weeks

[newlib] branch cygwin-3_5-branch updated (22474a6e5 -> 67b31bc4a)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch cygwin-3_5-branch in repository newlib. from 22474a6e5 Cygwin: check_dir_not_empty: Avoid leaving the allocated buffer. new c4102f82d Cygwin: lockf: Fix access violation in lf_clearlock(). new 67b31bc4a Cygwin: flock: Fix overlap handling in lf_setlock() and lf_cl [...] The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: winsup/cygwin/flock.cc | 37 ++++++++++++++++++++++--------------- winsup/cygwin/release/3.5.5 | 6 ++++++ 2 files changed, 28 insertions(+), 15 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 months, 3 weeks

[gcc] branch master updated (fa18217f60f -> 086ee8d0866)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from fa18217f60f RISC-V: Refine the rtl dump expand check for vector SAT_ADD new bf57f9b5990 testsuite: i386: Fix gcc.target/i386/pr117232-1.c etc. with [...] new 086ee8d0866 i386: Remove workaround for Solaris ld 64-bit TLS IE limitation The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/i386/i386.cc | 11 ----------- gcc/config/i386/i386.md | 17 ----------------- gcc/testsuite/gcc.target/i386/pr117232-1.c | 2 +- gcc/testsuite/gcc.target/i386/pr117232-apx-1.c | 2 +- 4 files changed, 2 insertions(+), 30 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 months, 3 weeks

[glibc] branch master updated (d899b48a30 -> 47311cca31)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository glibc. from d899b48a30 Fix femode_t conditionals for arc and or1k new e162ab2bf1 AArch64: Remove thunderx{,2} memcpy new f4d00dd60d AArch64: Add support for memory protection keys new 47311cca31 manual: Add description of AArch64-specific pkey flags The 3 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: manual/memory.texi | 16 +- sysdeps/aarch64/cpu-features.h | 8 - sysdeps/aarch64/multiarch/Makefile | 2 - sysdeps/aarch64/multiarch/ifunc-impl-list.c | 4 - sysdeps/aarch64/multiarch/memcpy.c | 8 - sysdeps/aarch64/multiarch/memcpy_thunderx.S | 305 -------------- sysdeps/aarch64/multiarch/memcpy_thunderx2.S | 457 --------------------- sysdeps/aarch64/multiarch/memmove.c | 8 - sysdeps/unix/sysv/linux/aarch64/Makefile | 3 + .../unix/sysv/linux/{x86 => aarch64}/arch-pkey.h | 37 +- sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h | 1 + sysdeps/unix/sysv/linux/aarch64/bits/mman.h | 8 + sysdeps/unix/sysv/linux/aarch64/pkey_get.c | 73 ++++ sysdeps/unix/sysv/linux/aarch64/pkey_set.c | 113 +++++ sysdeps/unix/sysv/linux/aarch64/tst-aarch64-pkey.c | 186 +++++++++ sysdeps/unix/sysv/linux/tst-pkey.c | 51 ++- 16 files changed, 464 insertions(+), 816 deletions(-) delete mode 100644 sysdeps/aarch64/multiarch/memcpy_thunderx.S delete mode 100644 sysdeps/aarch64/multiarch/memcpy_thunderx2.S copy sysdeps/unix/sysv/linux/{x86 => aarch64}/arch-pkey.h (53%) create mode 100644 sysdeps/unix/sysv/linux/aarch64/pkey_get.c create mode 100644 sysdeps/unix/sysv/linux/aarch64/pkey_set.c create mode 100644 sysdeps/unix/sysv/linux/aarch64/tst-aarch64-pkey.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 months, 3 weeks

[gcc] branch master updated (ff5a14abeb3 -> fa18217f60f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from ff5a14abeb3 tree-optimization/117574 - bougs niter lt-to-ne new 42f1a08e41d RISC-V: Rearrange the test files for vector SAT_ADD [NFC] new b95d585fd49 RISC-V: Introduce riscv/rvv/autovec/sat folder to rvv.exp t [...] new fa18217f60f RISC-V: Refine the rtl dump expand check for vector SAT_ADD The 3 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../riscv/rvv/autovec/binop/vec_sat_s_add-1.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-10.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-11.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-12.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-13.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-14.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-15.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-16.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-2.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-3.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-4.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-5.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-6.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-7.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-8.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-9.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_u_add-2.c | 9 ------- .../riscv/rvv/autovec/{ => sat}/vec_sat_arith.h | 0 .../{binop => sat}/vec_sat_binary_vvv_run.h | 0 .../{binop => sat}/vec_sat_binary_vvx_run.h | 0 .../autovec/{binop => sat}/vec_sat_binary_vx_run.h | 0 .../rvv/autovec/{binop => sat}/vec_sat_data.h | 0 .../riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c | 10 ++++++++ .../vec_sat_s_add-run-1-s16.c} | 2 +- .../vec_sat_s_add-run-1-s32.c} | 2 +- .../vec_sat_s_add-run-1-s64.c} | 2 +- .../vec_sat_s_add-run-1-s8.c} | 2 +- .../vec_sat_s_add-run-2-s16.c} | 2 +- .../vec_sat_s_add-run-2-s32.c} | 2 +- .../vec_sat_s_add-run-2-s64.c} | 2 +- .../vec_sat_s_add-run-2-s8.c} | 2 +- .../vec_sat_s_add-run-3-s16.c} | 2 +- .../vec_sat_s_add-run-3-s32.c} | 2 +- .../vec_sat_s_add-run-3-s64.c} | 2 +- .../vec_sat_s_add-run-3-s8.c} | 2 +- .../vec_sat_s_add-run-4-s16.c} | 2 +- .../vec_sat_s_add-run-4-s32.c} | 2 +- .../vec_sat_s_add-run-4-s64.c} | 2 +- .../vec_sat_s_add-run-4-s8.c} | 2 +- .../riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c | 28 ++++++++++++++++++++++ .../vec_sat_u_add-1-u32.c} | 4 ++-- .../vec_sat_u_add-1-u64.c} | 4 ++-- .../vec_sat_u_add-1.c => sat/vec_sat_u_add-1-u8.c} | 4 ++-- .../vec_sat_u_add-2-u16.c} | 4 ++-- .../vec_sat_u_add-2-u32.c} | 4 ++-- .../vec_sat_u_add-2-u64.c} | 4 ++-- .../vec_sat_u_add-5.c => sat/vec_sat_u_add-2-u8.c} | 4 ++-- .../vec_sat_u_add-3-u16.c} | 4 ++-- .../vec_sat_u_add-3-u32.c} | 4 ++-- .../vec_sat_u_add-3-u64.c} | 4 ++-- .../vec_sat_u_add-9.c => sat/vec_sat_u_add-3-u8.c} | 4 ++-- .../vec_sat_u_add-4-u16.c} | 4 ++-- .../vec_sat_u_add-4-u32.c} | 4 ++-- .../vec_sat_u_add-4-u64.c} | 4 ++-- .../vec_sat_u_add-4-u8.c} | 4 ++-- .../vec_sat_u_add-5-u16.c} | 4 ++-- .../vec_sat_u_add-5-u32.c} | 4 ++-- .../vec_sat_u_add-5-u64.c} | 4 ++-- .../vec_sat_u_add-5-u8.c} | 4 ++-- .../vec_sat_u_add-6-u16.c} | 4 ++-- .../vec_sat_u_add-6-u32.c} | 4 ++-- .../vec_sat_u_add-6-u64.c} | 4 ++-- .../vec_sat_u_add-6-u8.c} | 4 ++-- .../vec_sat_u_add-7-u16.c} | 4 ++-- .../vec_sat_u_add-7-u32.c} | 4 ++-- .../vec_sat_u_add-7-u64.c} | 4 ++-- .../vec_sat_u_add-7-u8.c} | 4 ++-- .../vec_sat_u_add-8-u16.c} | 4 ++-- .../vec_sat_u_add-8-u32.c} | 4 ++-- .../vec_sat_u_add-8-u64.c} | 4 ++-- .../vec_sat_u_add-8-u8.c} | 4 ++-- .../vec_sat_u_add-run-1-u16.c} | 2 +- .../vec_sat_u_add-run-1-u32.c} | 2 +- .../vec_sat_u_add-run-1-u64.c} | 2 +- .../vec_sat_u_add-run-1-u8.c} | 2 +- .../vec_sat_u_add-run-2-u16.c} | 2 +- .../vec_sat_u_add-run-2-u32.c} | 2 +- .../vec_sat_u_add-run-2-u64.c} | 2 +- .../vec_sat_u_add-run-2-u8.c} | 2 +- .../vec_sat_u_add-run-3-u16.c} | 2 +- .../vec_sat_u_add-run-3-u32.c} | 2 +- .../vec_sat_u_add-run-3-u64.c} | 2 +- .../vec_sat_u_add-run-3-u8.c} | 2 +- .../vec_sat_u_add-run-4-u16.c} | 2 +- .../vec_sat_u_add-run-4-u32.c} | 2 +- .../vec_sat_u_add-run-4-u64.c} | 2 +- .../vec_sat_u_add-run-4-u8.c} | 2 +- .../vec_sat_u_add-run-5-u16.c} | 2 +- .../vec_sat_u_add-run-5-u32.c} | 2 +- .../vec_sat_u_add-run-5-u64.c} | 2 +- .../vec_sat_u_add-run-5-u8.c} | 2 +- .../vec_sat_u_add-run-6-u16.c} | 2 +- .../vec_sat_u_add-run-6-u32.c} | 2 +- .../vec_sat_u_add-run-6-u64.c} | 2 +- .../vec_sat_u_add-run-6-u8.c} | 2 +- .../vec_sat_u_add-run-7-u16.c} | 2 +- .../vec_sat_u_add-run-7-u32.c} | 2 +- .../vec_sat_u_add-run-7-u64.c} | 2 +- .../vec_sat_u_add-run-7-u8.c} | 2 +- .../vec_sat_u_add-run-8-u16.c} | 2 +- .../vec_sat_u_add-run-8-u32.c} | 2 +- .../vec_sat_u_add-run-8-u64.c} | 2 +- .../vec_sat_u_add-run-8-u8.c} | 2 +- .../vec_sat_u_add_imm-1-u16.c} | 4 ++-- .../vec_sat_u_add_imm-1-u32.c} | 4 ++-- .../vec_sat_u_add_imm-1-u64.c} | 4 ++-- .../vec_sat_u_add_imm-1-u8.c} | 4 ++-- .../vec_sat_u_add_imm-2-u16.c} | 4 ++-- .../vec_sat_u_add_imm-2-u32.c} | 4 ++-- .../vec_sat_u_add_imm-2-u64.c} | 4 ++-- .../vec_sat_u_add_imm-2-u8.c} | 4 ++-- .../vec_sat_u_add_imm-3-u16.c} | 4 ++-- .../vec_sat_u_add_imm-3-u32.c} | 4 ++-- .../vec_sat_u_add_imm-3-u64.c} | 4 ++-- .../vec_sat_u_add_imm-3-u8.c} | 4 ++-- .../vec_sat_u_add_imm-4-u16.c} | 4 ++-- .../vec_sat_u_add_imm-4-u32.c} | 4 ++-- .../vec_sat_u_add_imm-4-u64.c} | 4 ++-- .../vec_sat_u_add_imm-4-u8.c} | 4 ++-- .../vec_sat_u_add_imm-run-1-u16.c} | 2 +- .../vec_sat_u_add_imm-run-1-u32.c} | 2 +- .../vec_sat_u_add_imm-run-1-u64.c} | 2 +- .../vec_sat_u_add_imm-run-1-u8.c} | 2 +- .../vec_sat_u_add_imm-run-2-u16.c} | 2 +- .../vec_sat_u_add_imm-run-2-u32.c} | 2 +- .../vec_sat_u_add_imm-run-2-u64.c} | 2 +- .../vec_sat_u_add_imm-run-2-u8.c} | 2 +- .../vec_sat_u_add_imm-run-3-u16.c} | 2 +- .../vec_sat_u_add_imm-run-3-u32.c} | 2 +- .../vec_sat_u_add_imm-run-3-u64.c} | 2 +- .../vec_sat_u_add_imm-run-3-u8.c} | 2 +- .../vec_sat_u_add_imm-run-4-u16.c} | 2 +- .../vec_sat_u_add_imm-run-4-u32.c} | 2 +- .../vec_sat_u_add_imm-run-4-u64.c} | 2 +- .../vec_sat_u_add_imm-run-4-u8.c} | 2 +- .../vec_sat_u_add_imm_reconcile-1-u16.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-1-u32.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-1-u64.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-1-u8.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-2-u16.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-2-u32.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-2-u64.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-2-u8.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-3-u16.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-3-u32.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-3-u64.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-3-u8.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-4-u16.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-4-u32.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-4-u8.c} | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 2 ++ 166 files changed, 378 insertions(+), 341 deletions(-) delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-1.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-10.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-11.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-12.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-13.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-14.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-15.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-16.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-2.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-3.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-4.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-5.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-6.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-7.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-8.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-9.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{ => sat}/vec_sat_arith.h (100%) copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop => sat}/vec_sat_binary_vvv_ [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop => sat}/vec_sat_binary_vvx_ [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop => sat}/vec_sat_binary_vx_r [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop => sat}/vec_sat_data.h (100%) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-2.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-3.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-4.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-1.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-6.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-7.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-8.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-5.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-10.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-11.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-12.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-9.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-14.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-15.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-16.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-13.c => [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-3.c => sat/ [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-4.c => sat/ [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-1.c => sat/ [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-6.c => sat/ [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-7.c => sat/ [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-8.c => sat/ [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-5.c => sat/ [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-10.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-11.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-12.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-9.c => sat/ [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-14.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-15.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-16.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-13.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-18.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-19.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-20.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-17.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-22.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-23.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-24.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-21.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-26.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-27.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-28.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-25.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-30.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-31.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-32.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-29.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-2.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-3.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-4.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-1.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-6.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-7.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-8.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-5.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-10.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-11.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-12.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-9.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-14.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-15.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-16.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-13.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-18.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-19.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-20.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-17.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-22.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-23.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-24.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-21.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-26.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-27.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-28.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-25.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-30.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-31.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-32.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-29.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-2.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-3.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-4.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-1.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-6.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-7.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-8.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-5.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-10.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-11.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-12.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-9.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-14.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-15.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-16.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-13.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-2.c [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-3.c [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-4.c [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-1.c [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-6.c [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-7.c [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-8.c [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-5.c [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-10. [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-11. [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-12. [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-9.c [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-14. [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-15. [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-16. [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-13. [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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Tcwg-commits November 2024