Tcwg-commits November 2024

tcwg-commits@lists.linaro.org

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1468 discussions

[binutils-gdb] branch master updated (661611b9d71 -> 4d1636909da)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from 661611b9d71 gdb/python: fix reference leak in gdb.BreakpointLocation.th [...] new 4d1636909da Remove Debian from SECURITY.txt The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: binutils/SECURITY.txt | 1 - 1 file changed, 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 days, 14 hours

[newlib] branch cygwin-3_5-branch updated (22474a6e5 -> 67b31bc4a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch cygwin-3_5-branch in repository newlib. from 22474a6e5 Cygwin: check_dir_not_empty: Avoid leaving the allocated buffer. new c4102f82d Cygwin: lockf: Fix access violation in lf_clearlock(). new 67b31bc4a Cygwin: flock: Fix overlap handling in lf_setlock() and lf_cl [...] The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: winsup/cygwin/flock.cc | 37 ++++++++++++++++++++++--------------- winsup/cygwin/release/3.5.5 | 6 ++++++ 2 files changed, 28 insertions(+), 15 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 days, 14 hours

[gcc] branch master updated (fa18217f60f -> 086ee8d0866)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from fa18217f60f RISC-V: Refine the rtl dump expand check for vector SAT_ADD new bf57f9b5990 testsuite: i386: Fix gcc.target/i386/pr117232-1.c etc. with [...] new 086ee8d0866 i386: Remove workaround for Solaris ld 64-bit TLS IE limitation The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/i386/i386.cc | 11 ----------- gcc/config/i386/i386.md | 17 ----------------- gcc/testsuite/gcc.target/i386/pr117232-1.c | 2 +- gcc/testsuite/gcc.target/i386/pr117232-apx-1.c | 2 +- 4 files changed, 2 insertions(+), 30 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 days, 15 hours

[glibc] branch master updated (d899b48a30 -> 47311cca31)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository glibc. from d899b48a30 Fix femode_t conditionals for arc and or1k new e162ab2bf1 AArch64: Remove thunderx{,2} memcpy new f4d00dd60d AArch64: Add support for memory protection keys new 47311cca31 manual: Add description of AArch64-specific pkey flags The 3 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: manual/memory.texi | 16 +- sysdeps/aarch64/cpu-features.h | 8 - sysdeps/aarch64/multiarch/Makefile | 2 - sysdeps/aarch64/multiarch/ifunc-impl-list.c | 4 - sysdeps/aarch64/multiarch/memcpy.c | 8 - sysdeps/aarch64/multiarch/memcpy_thunderx.S | 305 -------------- sysdeps/aarch64/multiarch/memcpy_thunderx2.S | 457 --------------------- sysdeps/aarch64/multiarch/memmove.c | 8 - sysdeps/unix/sysv/linux/aarch64/Makefile | 3 + .../unix/sysv/linux/{x86 => aarch64}/arch-pkey.h | 37 +- sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h | 1 + sysdeps/unix/sysv/linux/aarch64/bits/mman.h | 8 + sysdeps/unix/sysv/linux/aarch64/pkey_get.c | 73 ++++ sysdeps/unix/sysv/linux/aarch64/pkey_set.c | 113 +++++ sysdeps/unix/sysv/linux/aarch64/tst-aarch64-pkey.c | 186 +++++++++ sysdeps/unix/sysv/linux/tst-pkey.c | 51 ++- 16 files changed, 464 insertions(+), 816 deletions(-) delete mode 100644 sysdeps/aarch64/multiarch/memcpy_thunderx.S delete mode 100644 sysdeps/aarch64/multiarch/memcpy_thunderx2.S copy sysdeps/unix/sysv/linux/{x86 => aarch64}/arch-pkey.h (53%) create mode 100644 sysdeps/unix/sysv/linux/aarch64/pkey_get.c create mode 100644 sysdeps/unix/sysv/linux/aarch64/pkey_set.c create mode 100644 sysdeps/unix/sysv/linux/aarch64/tst-aarch64-pkey.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 days, 15 hours

[gcc] branch master updated (ff5a14abeb3 -> fa18217f60f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from ff5a14abeb3 tree-optimization/117574 - bougs niter lt-to-ne new 42f1a08e41d RISC-V: Rearrange the test files for vector SAT_ADD [NFC] new b95d585fd49 RISC-V: Introduce riscv/rvv/autovec/sat folder to rvv.exp t [...] new fa18217f60f RISC-V: Refine the rtl dump expand check for vector SAT_ADD The 3 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../riscv/rvv/autovec/binop/vec_sat_s_add-1.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-10.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-11.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-12.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-13.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-14.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-15.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-16.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-2.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-3.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-4.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-5.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-6.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-7.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-8.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_s_add-9.c | 9 ------- .../riscv/rvv/autovec/binop/vec_sat_u_add-2.c | 9 ------- .../riscv/rvv/autovec/{ => sat}/vec_sat_arith.h | 0 .../{binop => sat}/vec_sat_binary_vvv_run.h | 0 .../{binop => sat}/vec_sat_binary_vvx_run.h | 0 .../autovec/{binop => sat}/vec_sat_binary_vx_run.h | 0 .../rvv/autovec/{binop => sat}/vec_sat_data.h | 0 .../riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c | 10 ++++++++ .../riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c | 10 ++++++++ .../vec_sat_s_add-run-1-s16.c} | 2 +- .../vec_sat_s_add-run-1-s32.c} | 2 +- .../vec_sat_s_add-run-1-s64.c} | 2 +- .../vec_sat_s_add-run-1-s8.c} | 2 +- .../vec_sat_s_add-run-2-s16.c} | 2 +- .../vec_sat_s_add-run-2-s32.c} | 2 +- .../vec_sat_s_add-run-2-s64.c} | 2 +- .../vec_sat_s_add-run-2-s8.c} | 2 +- .../vec_sat_s_add-run-3-s16.c} | 2 +- .../vec_sat_s_add-run-3-s32.c} | 2 +- .../vec_sat_s_add-run-3-s64.c} | 2 +- .../vec_sat_s_add-run-3-s8.c} | 2 +- .../vec_sat_s_add-run-4-s16.c} | 2 +- .../vec_sat_s_add-run-4-s32.c} | 2 +- .../vec_sat_s_add-run-4-s64.c} | 2 +- .../vec_sat_s_add-run-4-s8.c} | 2 +- .../riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c | 28 ++++++++++++++++++++++ .../vec_sat_u_add-1-u32.c} | 4 ++-- .../vec_sat_u_add-1-u64.c} | 4 ++-- .../vec_sat_u_add-1.c => sat/vec_sat_u_add-1-u8.c} | 4 ++-- .../vec_sat_u_add-2-u16.c} | 4 ++-- .../vec_sat_u_add-2-u32.c} | 4 ++-- .../vec_sat_u_add-2-u64.c} | 4 ++-- .../vec_sat_u_add-5.c => sat/vec_sat_u_add-2-u8.c} | 4 ++-- .../vec_sat_u_add-3-u16.c} | 4 ++-- .../vec_sat_u_add-3-u32.c} | 4 ++-- .../vec_sat_u_add-3-u64.c} | 4 ++-- .../vec_sat_u_add-9.c => sat/vec_sat_u_add-3-u8.c} | 4 ++-- .../vec_sat_u_add-4-u16.c} | 4 ++-- .../vec_sat_u_add-4-u32.c} | 4 ++-- .../vec_sat_u_add-4-u64.c} | 4 ++-- .../vec_sat_u_add-4-u8.c} | 4 ++-- .../vec_sat_u_add-5-u16.c} | 4 ++-- .../vec_sat_u_add-5-u32.c} | 4 ++-- .../vec_sat_u_add-5-u64.c} | 4 ++-- .../vec_sat_u_add-5-u8.c} | 4 ++-- .../vec_sat_u_add-6-u16.c} | 4 ++-- .../vec_sat_u_add-6-u32.c} | 4 ++-- .../vec_sat_u_add-6-u64.c} | 4 ++-- .../vec_sat_u_add-6-u8.c} | 4 ++-- .../vec_sat_u_add-7-u16.c} | 4 ++-- .../vec_sat_u_add-7-u32.c} | 4 ++-- .../vec_sat_u_add-7-u64.c} | 4 ++-- .../vec_sat_u_add-7-u8.c} | 4 ++-- .../vec_sat_u_add-8-u16.c} | 4 ++-- .../vec_sat_u_add-8-u32.c} | 4 ++-- .../vec_sat_u_add-8-u64.c} | 4 ++-- .../vec_sat_u_add-8-u8.c} | 4 ++-- .../vec_sat_u_add-run-1-u16.c} | 2 +- .../vec_sat_u_add-run-1-u32.c} | 2 +- .../vec_sat_u_add-run-1-u64.c} | 2 +- .../vec_sat_u_add-run-1-u8.c} | 2 +- .../vec_sat_u_add-run-2-u16.c} | 2 +- .../vec_sat_u_add-run-2-u32.c} | 2 +- .../vec_sat_u_add-run-2-u64.c} | 2 +- .../vec_sat_u_add-run-2-u8.c} | 2 +- .../vec_sat_u_add-run-3-u16.c} | 2 +- .../vec_sat_u_add-run-3-u32.c} | 2 +- .../vec_sat_u_add-run-3-u64.c} | 2 +- .../vec_sat_u_add-run-3-u8.c} | 2 +- .../vec_sat_u_add-run-4-u16.c} | 2 +- .../vec_sat_u_add-run-4-u32.c} | 2 +- .../vec_sat_u_add-run-4-u64.c} | 2 +- .../vec_sat_u_add-run-4-u8.c} | 2 +- .../vec_sat_u_add-run-5-u16.c} | 2 +- .../vec_sat_u_add-run-5-u32.c} | 2 +- .../vec_sat_u_add-run-5-u64.c} | 2 +- .../vec_sat_u_add-run-5-u8.c} | 2 +- .../vec_sat_u_add-run-6-u16.c} | 2 +- .../vec_sat_u_add-run-6-u32.c} | 2 +- .../vec_sat_u_add-run-6-u64.c} | 2 +- .../vec_sat_u_add-run-6-u8.c} | 2 +- .../vec_sat_u_add-run-7-u16.c} | 2 +- .../vec_sat_u_add-run-7-u32.c} | 2 +- .../vec_sat_u_add-run-7-u64.c} | 2 +- .../vec_sat_u_add-run-7-u8.c} | 2 +- .../vec_sat_u_add-run-8-u16.c} | 2 +- .../vec_sat_u_add-run-8-u32.c} | 2 +- .../vec_sat_u_add-run-8-u64.c} | 2 +- .../vec_sat_u_add-run-8-u8.c} | 2 +- .../vec_sat_u_add_imm-1-u16.c} | 4 ++-- .../vec_sat_u_add_imm-1-u32.c} | 4 ++-- .../vec_sat_u_add_imm-1-u64.c} | 4 ++-- .../vec_sat_u_add_imm-1-u8.c} | 4 ++-- .../vec_sat_u_add_imm-2-u16.c} | 4 ++-- .../vec_sat_u_add_imm-2-u32.c} | 4 ++-- .../vec_sat_u_add_imm-2-u64.c} | 4 ++-- .../vec_sat_u_add_imm-2-u8.c} | 4 ++-- .../vec_sat_u_add_imm-3-u16.c} | 4 ++-- .../vec_sat_u_add_imm-3-u32.c} | 4 ++-- .../vec_sat_u_add_imm-3-u64.c} | 4 ++-- .../vec_sat_u_add_imm-3-u8.c} | 4 ++-- .../vec_sat_u_add_imm-4-u16.c} | 4 ++-- .../vec_sat_u_add_imm-4-u32.c} | 4 ++-- .../vec_sat_u_add_imm-4-u64.c} | 4 ++-- .../vec_sat_u_add_imm-4-u8.c} | 4 ++-- .../vec_sat_u_add_imm-run-1-u16.c} | 2 +- .../vec_sat_u_add_imm-run-1-u32.c} | 2 +- .../vec_sat_u_add_imm-run-1-u64.c} | 2 +- .../vec_sat_u_add_imm-run-1-u8.c} | 2 +- .../vec_sat_u_add_imm-run-2-u16.c} | 2 +- .../vec_sat_u_add_imm-run-2-u32.c} | 2 +- .../vec_sat_u_add_imm-run-2-u64.c} | 2 +- .../vec_sat_u_add_imm-run-2-u8.c} | 2 +- .../vec_sat_u_add_imm-run-3-u16.c} | 2 +- .../vec_sat_u_add_imm-run-3-u32.c} | 2 +- .../vec_sat_u_add_imm-run-3-u64.c} | 2 +- .../vec_sat_u_add_imm-run-3-u8.c} | 2 +- .../vec_sat_u_add_imm-run-4-u16.c} | 2 +- .../vec_sat_u_add_imm-run-4-u32.c} | 2 +- .../vec_sat_u_add_imm-run-4-u64.c} | 2 +- .../vec_sat_u_add_imm-run-4-u8.c} | 2 +- .../vec_sat_u_add_imm_reconcile-1-u16.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-1-u32.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-1-u64.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-1-u8.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-2-u16.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-2-u32.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-2-u64.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-2-u8.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-3-u16.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-3-u32.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-3-u64.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-3-u8.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-4-u16.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-4-u32.c} | 4 ++-- .../vec_sat_u_add_imm_reconcile-4-u8.c} | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 2 ++ 166 files changed, 378 insertions(+), 341 deletions(-) delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-1.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-10.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-11.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-12.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-13.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-14.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-15.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-16.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-2.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-3.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-4.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-5.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-6.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-7.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-8.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-9.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{ => sat}/vec_sat_arith.h (100%) copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop => sat}/vec_sat_binary_vvv_ [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop => sat}/vec_sat_binary_vvx_ [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop => sat}/vec_sat_binary_vx_r [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop => sat}/vec_sat_data.h (100%) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-2.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-3.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-4.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-1.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-6.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-7.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-8.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-5.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-10.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-11.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-12.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-9.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-14.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-15.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-16.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-13.c => [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-3.c => sat/ [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-4.c => sat/ [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-1.c => sat/ [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-6.c => sat/ [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-7.c => sat/ [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-8.c => sat/ [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-5.c => sat/ [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-10.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-11.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-12.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-9.c => sat/ [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-14.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-15.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-16.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-13.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-18.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-19.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-20.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-17.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-22.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-23.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-24.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-21.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-26.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-27.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-28.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-25.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-30.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-31.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-32.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-29.c => sat [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-2.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-3.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-4.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-1.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-6.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-7.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-8.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-5.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-10.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-11.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-12.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-9.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-14.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-15.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-16.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-13.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-18.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-19.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-20.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-17.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-22.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-23.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-24.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-21.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-26.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-27.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-28.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-25.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-30.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-31.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-32.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-run-29.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-2.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-3.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-4.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-1.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-6.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-7.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-8.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-5.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-10.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-11.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-12.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-9.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-14.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-15.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-16.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-13.c => [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-2.c [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-3.c [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-4.c [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-1.c [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-6.c [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-7.c [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-8.c [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-5.c [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-10. [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-11. [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-12. [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-9.c [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-14. [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-15. [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-16. [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm-run-13. [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add_imm_reconci [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 days, 16 hours

[newlib] branch main updated (b091b47b9 -> 5daf14f5f)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch main in repository newlib. from b091b47b9 cygthread: suspend thread before terminating. new b8d3dec49 newlib/libc/include/time.h: Removed clock_id casts new 5daf14f5f Remove accidental checkin of top-level file "test" The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: newlib/libc/include/time.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[newlib] branch main updated (b2672642c -> b091b47b9)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch main in repository newlib. from b2672642c Add Windows Server 2025 build number new b091b47b9 cygthread: suspend thread before terminating. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: winsup/cygwin/cygthread.cc | 14 ++++++++++++++ winsup/cygwin/pinfo.cc | 10 +++++++--- winsup/cygwin/sigproc.cc | 12 ++++++++++-- 3 files changed, 31 insertions(+), 5 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[newlib] branch master updated (b2672642c -> b091b47b9)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository newlib. from b2672642c Add Windows Server 2025 build number new b091b47b9 cygthread: suspend thread before terminating. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: winsup/cygwin/cygthread.cc | 14 ++++++++++++++ winsup/cygwin/pinfo.cc | 10 +++++++--- winsup/cygwin/sigproc.cc | 12 ++++++++++-- 3 files changed, 31 insertions(+), 5 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[gcc] branch master updated (ed6d0867fdb -> ff5a14abeb3)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from ed6d0867fdb Extend expand_absneg_bit to vector modes new ff5a14abeb3 tree-optimization/117574 - bougs niter lt-to-ne The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/testsuite/gcc.dg/torture/pr117574-1.c | 20 ++++++++++++++++++++ gcc/tree-ssa-loop-niter.cc | 31 +++++++------------------------ 2 files changed, 27 insertions(+), 24 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/torture/pr117574-1.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 days, 17 hours

[gcc] branch devel/existing-fp8 created (now d54a66c1d81)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch devel/existing-fp8 in repository gcc. at d54a66c1d81 Work in progress for refactoring simd intrinsic This branch includes the following new commits: new 1b6b028e272 aarch64: Refactor infrastructure for advsimd intrinsics new 3103441079f aarch64: Add support for fp8 convert and scale new ee10846d021 aarch64: Add support for fp8dot2 and fp8dot4 new 8e45a01d0fd aarch64: Add support for fp8fma instructions new d54a66c1d81 Work in progress for refactoring simd intrinsic The 5 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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Tcwg-commits November 2024