Tcwg-commits October 2024

tcwg-commits@lists.linaro.org

3 participants
1593 discussions

[gcc] branch master updated (a00a0e34b8a -> aa84020b2ed)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from a00a0e34b8a aarch64: Require SVE2 and/or SME2 for SVE FAMINMAX intrinsics new aa84020b2ed libiberty: Fix comment typos The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: include/safe-ctype.h | 2 +- libiberty/cplus-dem.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 weeks, 2 days

[newlib] branch master updated (7ed9adb35 -> c60788982)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository newlib. from 7ed9adb35 Cygwin: pipe: Switch pipe mode to blocking mode by default new c60788982 Cygwin: sigfe: Fix a bug that signal handler destroys fpu states The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: winsup/cygwin/release/3.6.0 | 3 ++ winsup/cygwin/scripts/gendef | 91 ++++++++++++++++++++++++-------------------- 2 files changed, 53 insertions(+), 41 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 weeks, 2 days

[newlib] branch main updated (7ed9adb35 -> c60788982)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch main in repository newlib. from 7ed9adb35 Cygwin: pipe: Switch pipe mode to blocking mode by default new c60788982 Cygwin: sigfe: Fix a bug that signal handler destroys fpu states The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: winsup/cygwin/release/3.6.0 | 3 ++ winsup/cygwin/scripts/gendef | 91 ++++++++++++++++++++++++-------------------- 2 files changed, 53 insertions(+), 41 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 weeks, 2 days

[newlib] branch main updated (1f05c0405 -> 7ed9adb35)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch main in repository newlib. from 1f05c0405 Cygwin: pipe: fix shift value new 7ed9adb35 Cygwin: pipe: Switch pipe mode to blocking mode by default The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: winsup/cygwin/dtable.cc | 5 +- winsup/cygwin/fhandler/pipe.cc | 665 +++++++++++--------------------- winsup/cygwin/local_includes/fhandler.h | 44 +-- winsup/cygwin/local_includes/sigproc.h | 1 - winsup/cygwin/release/3.6.0 | 3 + winsup/cygwin/select.cc | 46 +-- winsup/cygwin/sigproc.cc | 10 - winsup/cygwin/spawn.cc | 4 - 8 files changed, 259 insertions(+), 519 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 weeks, 2 days

[newlib] branch master updated (1f05c0405 -> 7ed9adb35)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository newlib. from 1f05c0405 Cygwin: pipe: fix shift value new 7ed9adb35 Cygwin: pipe: Switch pipe mode to blocking mode by default The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: winsup/cygwin/dtable.cc | 5 +- winsup/cygwin/fhandler/pipe.cc | 665 +++++++++++--------------------- winsup/cygwin/local_includes/fhandler.h | 44 +-- winsup/cygwin/local_includes/sigproc.h | 1 - winsup/cygwin/release/3.6.0 | 3 + winsup/cygwin/select.cc | 46 +-- winsup/cygwin/sigproc.cc | 10 - winsup/cygwin/spawn.cc | 4 - 8 files changed, 259 insertions(+), 519 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 weeks, 2 days

[newlib] branch cygwin-3_5-branch updated (2962922d0 -> ea01b87f0)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch cygwin-3_5-branch in repository newlib. from 2962922d0 Add recent pipe change to release note new ea01b87f0 Cygwin: cygfe: Fix a bug that signal handler destroys fpu states The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: winsup/cygwin/release/3.5.5 | 3 +++ winsup/cygwin/scripts/gendef | 15 +++++++-------- 2 files changed, 10 insertions(+), 8 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 weeks, 2 days

[gcc] branch releases/gcc-14 updated (0e132a3b951 -> 8ac2f3ce09c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch releases/gcc-14 in repository gcc. from 0e132a3b951 Daily bump. new 4e174ac8ee9 Fix function multiversioning dispatcher link error with LTO new 8ac2f3ce09c aarch64: Forbid F64MM permutes in streaming mode The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/aarch64/aarch64-sve-builtins-base.def | 13 +++++-------- gcc/config/aarch64/aarch64.cc | 7 +++++++ gcc/testsuite/g++.target/aarch64/sve/aarch64-ssve.exp | 6 ++++++ gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_bf16.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_f16.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_f32.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_f64.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_s16.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_s32.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_s64.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_s8.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_u16.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_u32.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_u64.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_u8.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_bf16.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_f16.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_f32.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_f64.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_s16.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_s32.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_s64.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_s8.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_u16.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_u32.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_u64.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_u8.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_bf16.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_f16.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_f32.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_f64.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_s16.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_s32.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_s64.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_s8.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_u16.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_u32.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_u64.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_u8.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_bf16.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_f16.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_f32.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_f64.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_s16.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_s32.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_s64.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_s8.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_u16.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_u32.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_u64.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_u8.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_bf16.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_f16.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_f32.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_f64.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_s16.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_s32.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_s64.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_s8.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_u16.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_u32.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_u64.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_u8.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_bf16.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_f16.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_f32.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_f64.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_s16.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_s32.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_s64.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_s8.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_u16.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_u32.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_u64.c | 1 + gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_u8.c | 1 + 75 files changed, 90 insertions(+), 8 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 weeks, 2 days

[gcc] branch master updated (2a4ee57b043 -> a00a0e34b8a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 2a4ee57b043 testsuite: fix c23-constexpr-2a.c test to use dg-do run new 94b9ffbdd9a aarch64: Forbid F64MM permutes in streaming mode new e1b17a0cfd3 aarch64: Move ENTRY_VHSDF to aarch64-simd-pragma-builtins.def new ede97598e2c aarch64: Record separate streaming and non-streaming ISA re [...] new a00a0e34b8a aarch64: Require SVE2 and/or SME2 for SVE FAMINMAX intrinsics The 4 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config.gcc | 2 +- gcc/config/aarch64/aarch64-builtins.cc | 142 ++++++++++----------- gcc/config/aarch64/aarch64-protos.h | 87 ++++++++++++- .../aarch64/aarch64-simd-pragma-builtins.def | 14 +- gcc/config/aarch64/aarch64-sve-builtins-base.cc | 4 - gcc/config/aarch64/aarch64-sve-builtins-base.def | 36 ++---- gcc/config/aarch64/aarch64-sve-builtins-sme.def | 30 ++--- gcc/config/aarch64/aarch64-sve-builtins-sve2.cc | 4 + gcc/config/aarch64/aarch64-sve-builtins-sve2.def | 48 +++---- gcc/config/aarch64/aarch64-sve-builtins.cc | 51 +++++--- gcc/config/aarch64/aarch64-sve-builtins.h | 13 +- .../g++.target/aarch64/sve/aarch64-ssve.exp | 6 + .../gcc.target/aarch64/sve/acle/asm/trn1q_bf16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/trn1q_f16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/trn1q_f32.c | 1 + .../gcc.target/aarch64/sve/acle/asm/trn1q_f64.c | 1 + .../gcc.target/aarch64/sve/acle/asm/trn1q_s16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/trn1q_s32.c | 1 + .../gcc.target/aarch64/sve/acle/asm/trn1q_s64.c | 1 + .../gcc.target/aarch64/sve/acle/asm/trn1q_s8.c | 1 + .../gcc.target/aarch64/sve/acle/asm/trn1q_u16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/trn1q_u32.c | 1 + .../gcc.target/aarch64/sve/acle/asm/trn1q_u64.c | 1 + .../gcc.target/aarch64/sve/acle/asm/trn1q_u8.c | 1 + .../gcc.target/aarch64/sve/acle/asm/trn2q_bf16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/trn2q_f16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/trn2q_f32.c | 1 + .../gcc.target/aarch64/sve/acle/asm/trn2q_f64.c | 1 + .../gcc.target/aarch64/sve/acle/asm/trn2q_s16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/trn2q_s32.c | 1 + .../gcc.target/aarch64/sve/acle/asm/trn2q_s64.c | 1 + .../gcc.target/aarch64/sve/acle/asm/trn2q_s8.c | 1 + .../gcc.target/aarch64/sve/acle/asm/trn2q_u16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/trn2q_u32.c | 1 + .../gcc.target/aarch64/sve/acle/asm/trn2q_u64.c | 1 + .../gcc.target/aarch64/sve/acle/asm/trn2q_u8.c | 1 + .../gcc.target/aarch64/sve/acle/asm/uzp1q_bf16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/uzp1q_f16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/uzp1q_f32.c | 1 + .../gcc.target/aarch64/sve/acle/asm/uzp1q_f64.c | 1 + .../gcc.target/aarch64/sve/acle/asm/uzp1q_s16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/uzp1q_s32.c | 1 + .../gcc.target/aarch64/sve/acle/asm/uzp1q_s64.c | 1 + .../gcc.target/aarch64/sve/acle/asm/uzp1q_s8.c | 1 + .../gcc.target/aarch64/sve/acle/asm/uzp1q_u16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/uzp1q_u32.c | 1 + .../gcc.target/aarch64/sve/acle/asm/uzp1q_u64.c | 1 + .../gcc.target/aarch64/sve/acle/asm/uzp1q_u8.c | 1 + .../gcc.target/aarch64/sve/acle/asm/uzp2q_bf16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/uzp2q_f16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/uzp2q_f32.c | 1 + .../gcc.target/aarch64/sve/acle/asm/uzp2q_f64.c | 1 + .../gcc.target/aarch64/sve/acle/asm/uzp2q_s16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/uzp2q_s32.c | 1 + .../gcc.target/aarch64/sve/acle/asm/uzp2q_s64.c | 1 + .../gcc.target/aarch64/sve/acle/asm/uzp2q_s8.c | 1 + .../gcc.target/aarch64/sve/acle/asm/uzp2q_u16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/uzp2q_u32.c | 1 + .../gcc.target/aarch64/sve/acle/asm/uzp2q_u64.c | 1 + .../gcc.target/aarch64/sve/acle/asm/uzp2q_u8.c | 1 + .../gcc.target/aarch64/sve/acle/asm/zip1q_bf16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/zip1q_f16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/zip1q_f32.c | 1 + .../gcc.target/aarch64/sve/acle/asm/zip1q_f64.c | 1 + .../gcc.target/aarch64/sve/acle/asm/zip1q_s16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/zip1q_s32.c | 1 + .../gcc.target/aarch64/sve/acle/asm/zip1q_s64.c | 1 + .../gcc.target/aarch64/sve/acle/asm/zip1q_s8.c | 1 + .../gcc.target/aarch64/sve/acle/asm/zip1q_u16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/zip1q_u32.c | 1 + .../gcc.target/aarch64/sve/acle/asm/zip1q_u64.c | 1 + .../gcc.target/aarch64/sve/acle/asm/zip1q_u8.c | 1 + .../gcc.target/aarch64/sve/acle/asm/zip2q_bf16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/zip2q_f16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/zip2q_f32.c | 1 + .../gcc.target/aarch64/sve/acle/asm/zip2q_f64.c | 1 + .../gcc.target/aarch64/sve/acle/asm/zip2q_s16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/zip2q_s32.c | 1 + .../gcc.target/aarch64/sve/acle/asm/zip2q_s64.c | 1 + .../gcc.target/aarch64/sve/acle/asm/zip2q_s8.c | 1 + .../gcc.target/aarch64/sve/acle/asm/zip2q_u16.c | 1 + .../gcc.target/aarch64/sve/acle/asm/zip2q_u32.c | 1 + .../gcc.target/aarch64/sve/acle/asm/zip2q_u64.c | 1 + .../gcc.target/aarch64/sve/acle/asm/zip2q_u8.c | 1 + .../gcc.target/aarch64/sve/acle/general/amin_1.c | 9 ++ .../gcc.target/aarch64/sve2/acle/asm/amax_f16.c | 5 +- .../gcc.target/aarch64/sve2/acle/asm/amax_f32.c | 5 +- .../gcc.target/aarch64/sve2/acle/asm/amax_f64.c | 5 +- .../gcc.target/aarch64/sve2/acle/asm/amin_f16.c | 5 +- .../gcc.target/aarch64/sve2/acle/asm/amin_f32.c | 5 +- .../gcc.target/aarch64/sve2/acle/asm/amin_f64.c | 5 +- 91 files changed, 362 insertions(+), 186 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/amin_1.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 weeks, 2 days

[toolchain/ci/interesting-commits] branch master updated (797e67239 -> bea2e3ac8)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch master in repository toolchain/ci/interesting-commits. from 797e67239 Add entry 70c3db511ba14ff5fa68cb41d0714a9fb957ea5d from https [...] new bea2e3ac8 Add entry 70c3db511ba14ff5fa68cb41d0714a9fb957ea5d from https [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/sha1/70c3db511ba14ff5fa68cb41d0714a9fb957ea5d/commit-log.txt | 2 +- gcc/sha1/70c3db511ba14ff5fa68cb41d0714a9fb957ea5d/jira/description | 4 ++-- gcc/sha1/70c3db511ba14ff5fa68cb41d0714a9fb957ea5d/jira/summary | 2 +- gcc/sha1/70c3db511ba14ff5fa68cb41d0714a9fb957ea5d/jira/yaml | 6 +++--- gcc/sha1/70c3db511ba14ff5fa68cb41d0714a9fb957ea5d/status.txt | 2 +- .../gnu-aarch64-master-O2_LTO/reproduction_instructions.txt | 4 ++-- .../reproduction_instructions_with_ci_script.txt | 4 ++-- .../gnu-aarch64-master-O2_LTO/status.txt | 2 +- .../tcwg_bmk-code_size-cpu2017fast/status.txt | 2 +- 9 files changed, 14 insertions(+), 14 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 weeks, 2 days

[toolchain/ci/interesting-commits] branch master updated (496c6c3d1 -> 797e67239)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch master in repository toolchain/ci/interesting-commits. from 496c6c3d1 Add entry a88d6c6d777ad7c9235e2e620318f26e5347e50a from https [...] new 797e67239 Add entry 70c3db511ba14ff5fa68cb41d0714a9fb957ea5d from https [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../tcwg_bmk-code_size-cpu2017fast/gnu-aarch64-master-O2_LTO/build_url | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 weeks, 2 days

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Tcwg-commits October 2024