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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bootstrap_build/master-aarch64-bootstrap_debug
in repository toolchain/ci/base-artifacts.
from 0fc95feb6a 19: onsuccess: #21: 1: [TCWG CI] https://ci.linaro.org/job/t [...]
new d1e672777b 20: onsuccess: #22: 1: [TCWG CI] https://ci.linaro.org/job/t [...]
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Summary of changes:
01-reset_artifacts/console.log.xz | Bin 1884 -> 1908 bytes
02-prepare_abe/console.log.xz | Bin 2492 -> 2508 bytes
04-build_abe-bootstrap_debug/console.log.xz | Bin 267020 -> 266872 bytes
.../make-gcc-stage2.log.xz | Bin 217044 -> 216512 bytes
05-check_regression/console.log.xz | Bin 468 -> 468 bytes
git/gcc_rev | 2 +-
manifest.sh | 8 ++++----
7 files changed, 5 insertions(+), 5 deletions(-)
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unknown user pushed a change to branch master
in repository gcc.
from c48d7a6e320 RISC-V: Add RVV FMA auto-vectorization support
new ff313e1c74b RISC-V: Remove redundant printf of abs-run.c
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Summary of changes:
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c | 1 -
1 file changed, 1 deletion(-)
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unknown user pushed a change to branch master
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from f8af48d8755 RISC-V: Fix ternary instruction attribute bug
new c48d7a6e320 RISC-V: Add RVV FMA auto-vectorization support
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Summary of changes:
gcc/config/riscv/autovec.md | 65 +++++++++++++
gcc/config/riscv/riscv-protos.h | 2 +
gcc/config/riscv/riscv-v.cc | 20 ++++
.../gcc.target/riscv/rvv/autovec/ternop/ternop-1.c | 28 ++++++
.../gcc.target/riscv/rvv/autovec/ternop/ternop-2.c | 34 +++++++
.../gcc.target/riscv/rvv/autovec/ternop/ternop-3.c | 33 +++++++
.../riscv/rvv/autovec/ternop/ternop_run-1.c | 84 +++++++++++++++++
.../riscv/rvv/autovec/ternop/ternop_run-2.c | 104 +++++++++++++++++++++
.../riscv/rvv/autovec/ternop/ternop_run-3.c | 104 +++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 2 +
10 files changed, 476 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c
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unknown user pushed a change to branch master
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from c0df96b3cda RISC-V: Fix incorrect VXRM configuration in mode switching [...]
new f8af48d8755 RISC-V: Fix ternary instruction attribute bug
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gcc/config/riscv/vector.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_build/master-aarch64
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from 7b253ffffb 36: onsuccess: #39: 1: [TCWG CI] https://ci.linaro.org/job/t [...]
new ffbff70a2f 37: onsuccess: #40: 1: [TCWG CI] https://ci.linaro.org/job/t [...]
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Summary of changes:
01-reset_artifacts/console.log.xz | Bin 1888 -> 1860 bytes
02-prepare_abe/console.log.xz | Bin 2512 -> 2488 bytes
04-build_abe-gcc/console.log.xz | Bin 206352 -> 207084 bytes
04-build_abe-gcc/make-gcc-stage2.log.xz | Bin 173832 -> 174556 bytes
05-check_regression/console.log.xz | Bin 468 -> 468 bytes
06-update_baseline/console.log | 34 ++++++++++++++++----------------
git/gcc_rev | 2 +-
manifest.sh | 8 ++++----
8 files changed, 22 insertions(+), 22 deletions(-)
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unknown user pushed a change to branch master
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from 272f920b78f RISC-V: Add ZVFHMIN extension to the -march= option
new c0df96b3cda RISC-V: Fix incorrect VXRM configuration in mode switching [...]
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Summary of changes:
gcc/config/riscv/riscv.cc | 29 +++++++++++++++++++++-
.../riscv/rvv/base/{vxrm-8.c => vxrm-11.c} | 8 +++---
.../riscv/rvv/base/{vxrm-8.c => vxrm-12.c} | 6 ++---
3 files changed, 36 insertions(+), 7 deletions(-)
copy gcc/testsuite/gcc.target/riscv/rvv/base/{vxrm-8.c => vxrm-11.c} (61%)
copy gcc/testsuite/gcc.target/riscv/rvv/base/{vxrm-8.c => vxrm-12.c} (61%)
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